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Features
* * * * * * * * * * * * *
Maximum Supply Voltage 40V One Programmable/Adjustable Boost Converter Two Programmable Buck Converters One Programmable Linear Regulator OTP Customer Mode 16-bit Serial Interface Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality) Watchdog Various Diagnosis Functions 5 Voltage Sources Tailored to Resistor Measurement Charge Pump Small, 44-pin Package ESD Protection Against 2kV and 4kV
Airbag Power Supply IC ATA6264 Preliminary
1. Description
With the introduction of the ATA6264, Atmel(R) introduces a new generation of airbag power supplies for future airbag systems tailored to the needs of the automotive industry. It is designed in Atmel's 0.8 micron BCDMOS technology. ATA6264 contains all the necessary blocks to supply the microcontroller, the firing capacitors, and peripheral components of the airbag system. The power supply specifically fulfills the power requirements of dual-voltage microcontrollers used in modern ECUs. The integrated watchdog and diagnosis blocks additionally support the safety aspects. The 8-MHz 16-bit SPI enables a high communication speed. Despite the high-level functionality, ATA6264 comes in a space-saving QFP44 package.
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Figure 1-1.
Block Diagram
SVSAT VBATT VSAT
CP_OUT
SCLK
MOSI
MISO
SSQ
RESQ RESQ2 GNDD
K15
CP
Serial Interface Watchdog Reset
CP Logic
GKEYLogic
K30
GEVZ TxD1 RxD1 TxD2 RxD2 K1 K2 ISO9141 COMEVZO SVSAT COMSATO IASG1 IASG2 IASG3 IASG4 IASG5 ISENS SVPERI VPERIRegulator VPERI IASG VSAT VSATRegulator EVZ FBEVZ EVZRegulator OCEVZ GNDB
VEVZ
COMSATI
VVSAT
VVPERI
SVCORE UZP UZP AMUX VCORE
VVCORE
GNDA USP Internal Supply Reference VCORERegulator COMCOI
VINT
IREF
VBATT
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USP
COMCOO
ATA6264 [Preliminary]
1.1
1.1.1
Block Description
Integrated Boost Converter EVZ With an external n-channel FET, the integrated boost converter EVZ provides 3 different voltages adjustable via the serial interface for the energy reserve and firing capacitors. Two voltages are fixed values; one voltage can be adjusted using an external resistive divider. Integrated Buck Converter VSAT The integrated buck converter VSAT is a fully integrated step-down converter supplied by the boost converter, EVZ, and providing 7.8V, 9.1V, or 10.4V. The user can program the voltage via an OTP system. Integrated Buck Converter VCORE The integrated buck converter VCORE is a fully integrated step-down converter supplied either by the boost converter, EVZ, or by the battery, and providing 1.88V, 2.5V, or 5V. The user can program the voltage via an OTP system. Linear Regulator VPERI The linear regulator, VPERI, is supplied from the buck converter VSAT and provides an accurate voltage of 3.3V 3% or 5V 4% as a supply for sensitive elements such as sensors and ADC references with the current capability of 100 mA. The user can program the voltage via an OTP system. With a sophisticated power-sequencing concept of VCORE and VPERI, ATA6264 supports dual-voltage-supply microcontrollers, so that under all conditions the voltage difference between the two linear regulator voltages never drops below a defined value. This measure guarantees the safe operation of the system. Blocks Included * A general purpose comparator USP, for, for example, low battery voltage detection * A band gap as reference for all internal voltages and currents * Two ISO9141 interfaces, one of which is configurable via OTP in accordance with the LIN specification * Five constant voltage sources with current-to-voltage mirrors used for resistance measurements, such as buckle switch detection in the range from -0.5 mA to -40 mA * An AMUX block with push-pull buffer stage provides the output of all analog values such as voltage sources, low voltage detection, or the chip temperature for continuous diagnosis * A 16-bit serial interface for the communication with the microcontroller which includes a 16-bit shift register, a 16-bit latch, and a decoder-logic block * A watchdog to monitor the microcontroller and to generate reset signals in the case of failure * Internal oscillator generates internal clock signals * GKEY function to control the main switch of the ECU via a logic signal
1.1.2
1.1.3
1.1.4
1.1.5
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2. Pin Configuration
Figure 2-1. Pinning QFP44
COMEVZO GNDB GEVZ OCEVZ FBEVZ CP SVCORE CP-OUT COMCOO COMCOI COMSATO
USP K30 K1 K2 IASG1 IASG2 IASG3 IASG4 IASG5 ISENS TxD1
1 2 3 4 5 6 7 8 9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22
K15 EVZ SVSAT VSAT GNDD VINT COMSATI VCORE GNDA SVPERI VPERI
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Pin Description
Symbol USP K30 K1 K2 IASG1 IASG2 IASG3 IASG4 IASG5 ISENS TXD1 RESQ RXD2 RXD1 TXD2 MISO SSQ SCLK MOSI RESQ2 IREF UZP Function Comparator input Continuous connection to the car battery Bus line of 1st ISO9141 interface Bus line of 2nd ISO9141 interface Output of voltage source 1 Output of voltage source 2 Output of voltage source 3 Output of voltage source 4 Output of voltage source 5 Output of the current mirror from the IASGx interface Data input of the 1st ISO9141 interface Reset output Data output of the 2nd ISO9141 interface Data output of the 1st ISO9141 interface Data input of the 2nd ISO9141 interface Data output of the serial interface Chip select of the serial interface Clock input of the serial interface Data input of the serial Interface Redundant reset output Connection for the external reference resistor Analog measurement output
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RESQ RxD2 RxD1 TxD2 MISO SSQ SCLK MOSI RESQ2 IREF UZP
ATA6264 [Preliminary]
Table 2-1.
Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Description
Symbol VPERI SVPERI GNDA VCORE COMSATI VINT GNDD VSAT SVSAT EVZ K15 COMSATO COMCOI COMCOO CP-OUT SVCORE CP FBEVZ OCEVZ GEVZ GNDB COMEVZO Function Input for the VPERI regulator, internally used VPERI supply Output of VPERI regulator power transistor Analog GND Input for VCORE regulator Input of the VSAT externally compensated error amplifier Output of internal supply voltage Digital GND Input for VSAT regulator, internally used VSAT supply Output of VSAT regulator power transistor Input for EVZ regulator, internally used EVZ supply Connection to car battery via the ignition key Output of the VSAT externally compensated error amplifier Input of the VCORE externally compensated error amplifier Output of the VCORE externally compensated error amplifier Switchable output of charge pump voltage Output of VCORE regulator power transistor Charge pump output Input for external resistor divider to adjust EVZ voltage Input for overcurrent measurement of the EVZ regulator Gate driver output for the external FET of the EVZ regulator GND connection of all power stages Output of the EVZ externally compensated error amplifier
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3. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins. Parameters Remark Any combination of one or more pins applied with any voltage between the limits -0.3 K30 and K15 connected via diode to VBatt. USP connected via minimum 5 k to VBatt (maximum reverse current 5 mA). Any combination of one or more pins applied with any voltage between the limits Any combination of one or more pins applied with any voltage between the limits Any combination of one or more pins applied with any voltage between the limits Any combination of one or more pins applied with any voltage between the limits Any combination of one or more pins applied with any voltage between the limits Any combination of one or more pins applied with any voltage between the limits -25 Voltage necessary to drive -40 mA stored in 20 H -0.3 +45 V +45 V Minimum Maximum Unit
Voltage at pins, connected directly or indirectly to the car battery (K30, K15, USP)
Voltage at pins, connected directly or indirectly to the car battery (K1, K2) Voltage at pins, connected directly or indirectly to the car battery (IASG1, IASG2, IASG3, IASG4, IASG5) Voltage at ECU internal pins (FBEVZ, EVZ, VSAT) Maximum rate of change at pin VSAT Voltage at ECU internal pins (SVSAT, SVCORE) Voltage at ECU internal pins (CP, CP-OUT) Voltage at ECU internal pins (GEVZ, OCEVZ)
45
V
+45 1
V V/s V
-1
+45
-0.3
+56
V
-0.3
+10
V
Voltage at ECU internal pins (COMEVZO, COMSATO, COMSATI, VPERI, SVPERI, These voltages can be applied in any VCORE, COMCOI, COMCOO, IREF, UZP, combination with any voltage between the ISENS, RXD1, TXD1, RXD2, TXD2, limits RESQ, RESQ2, MISO, MOSI, SSQ, SCLK, VINT) Current at logic pins ESD classification at pins connected to devices outside the ECU (K30, K15) Human body model (HBM) HBM AEC Q100-002 Connected to voltages outside of maximum voltage ratings via resistor
-0.3
+7
V
-3
+3
mA
4000
V
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ATA6264 [Preliminary]
3. Absolute Maximum Ratings (Continued)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins. Parameters ESD classification at pins connected to devices outside the ECU (IASG1 to IASG5) Human body model (HBM) ESD classification at pins connected to devices outside the ECU (K1 and K2) Human body model (HBM) General ESD classification for all other pins Human body model (HBM) HBM AEC Q100-002 1500 V HBM AEC Q100-002 2500 V HBM AEC Q100-002 3000 V Remark Minimum Maximum Unit
Charged device model (CDM) - no corner CDM pins ESD STM5.3.1-1999 Charged device model (CDM) - corner pins
500
V
750
V
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4. Functional Range
Within the functional range, the ATA6264 works as specified. All voltages are referenced to the ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins. At the beginning of each specification table, supply voltage and temperature conditions are described.
Table 4-1.
Electrical Characteristics - Functional Range
Test Conditions Pin Symbol Min. -0.3 -25 Typ. Max. +40 +40 50 -0.3 -0.3 -0.3 -0.3 -0.3 -1.0 +40 +14 +5.5 +50 +5.5 +40 Unit V V V/s V V V V V V Type*
No. Parameters 1.1 Voltage on pins K30, K15, USP Rate of supply voltage rise (K30, K15, K1, K2) Supply voltage EVZ Supply voltage VSAT Supply voltages VCORE, VPERI Supply voltage CP, CP-OUT Voltage on digital I/O pins Voltage on pins SVSAT, SVCORE Voltage on pins UZP, ISENS, COMCOI, COMCOO, COMSATO, COMSATI, COMEVZO, FBEVZ, IREF, VINT Voltage on pins GEVZ, OCEVZ
1.1a Voltage on pins K1, K2 1.2 1.3 1.4 1.5 1.6 1.7 1.8
1.9
-0.3
+5.5
V
1.10
-0.3 -0.3 Voltage necessary to drive -40 mA stored in 20 H - 40 - 40 - 55
+10 +6
V V
1.11 Voltage on pin SVPERI Voltage on pins IASGx 1.12 (x = 1 to 5) Temperatures: Operating ambient temperature range 1.14 Operating junction temperature range Storage ambient/junction temperature range 1.15 Thermal resistance junction ambient
40
V
+ 90 +150 +105
C C C
60
K/W
Substrate current which can be drawn without 1.16 disturbances to upper defined blocks/functions(1) Note: 1. No substrate current occurs at pins K1, K2 down to VK1, VK2 > -25V
-40
mA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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ATA6264 [Preliminary]
4.1 Protection Against Substrate Currents
Due to the fact that the ATA6264 is connected to the wiring harness and to components outside of the ECU, negative voltages at the following pins might occur: * IASG interface: * USP comparator: IASG1, IASG2, IASG3, IASG4, IASG5 USP
If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen: * No disturbance of RESET block. * No voltage changes of any regulators outside of their tolerances. * No impact on digital circuitry (for example, changes of latches, status register, etc.) * No latch up of any circuitry
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5. Supply Currents
A minimum current has to flow into each pin for proper functioning of the IC.
Table 5-1.
Electrical Characteristics - Supply currents
Test Conditions Standby mode: 0V = VK30 = 18V, VK15 = 3V and KEYLATCH = OFF Standby mode: 18V < VK30 = 40V, VK15 = 3V and KEYLATCH = OFF Startup mode: 0V < VK30 = 18V, VK15 > 4.15V or KEYLATCH = ON, VEVZ = 0V, CCP = 47 nF Startup mode: 18V < VK30 = 40V VK15 > 4.15V or KEYLATCH = ON VEVZ = 0V, CCP = 47 nF Normal mode: 0V < VK30 = 18V, VEVZ > VK30, VK15 > 4V or KEYLATCH = ON, SVCORE open, AMUX Measurement K30 active Normal mode: 18V < VK30 = 40V, VEVZ > VK30, VK15 > 4.15V or KEYLATCH = ON, SVCORE open, AMUX Measurement K30 active Startup mode: 0V < VEVZ = 40V, VSAT = VPERI = VCORE = 0V, VK30 > 5V, VK15 > 4.15V, SVCORE and SVSAT open Normal mode: 0V < VEVZ = 40V, VPERI and VCORE > Reset Threshold, VEVZ > VK30, VSAT = 10V, VK30 > 5V, VK15 > 4.15V, SVCORE and SVSAT open, AMUX Measurement EVZ active Autonomous mode: 0V < VEVZ = 40V, VPERI and VCORE > Reset Threshold, VEVZ > VK30, VSAT = 10V, VK30 < 3.85V, VK15 < 3V, SVCORE and SVSAT open, AMUX Measurement EVZ active 0V < VSAT = 14V, SVPERI open, AMUX measurement VSAT active 0V < VPERI = 5.3V, AMUX measurement VPERI active 0V < VCORE = 5.3V, AMUX measurement VCORE active Pin K30 K30 Symbol
IK30 IK30
No. Parameters 2.1 Supply current at K30
Min. 0 0
Typ.
Max. 50 5
Unit A mA
Type* A A
2.1a Supply current at K30
2.1b Supply current at K30
K30
IK30
0
7
mA
A
2.1c Supply current at K30
K30
IK30
0
10
mA
A
2.1d Supply current at K30
K30
IK30
0
6.5
mA
A
2.1e Supply current at K30
K30
IK30
0
10
mA
A
2.2
Supply current at EVZ
EVZ
IEVZ
0
5
mA
A
2.2a Supply current at EVZ
EVZ
IEVZ
0
6
mA
A
2.2b Supply current at EVZ
EVZ
IEVZ
0
10
mA
A
2.3 2.4 2.5
Supply current at VSAT Supply current at VPERI Supply current at VCORE
VSAT VPERI VCORE
IVSAT IVPERI IVCORE
0 -0.2 -0.45
1.5 2.2 1
mA mA mA
A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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ATA6264 [Preliminary]
5.1 Discharger Circuit
Applications using the ATA6264 usually use a reverse polarity protection diode (D1 in Figure 5-1) in the power supply to prevent any damage if the wrong polarity is applied to VK30. Unfortunately, this method includes some risk as can be seen in the following description: During Standby mode (VK15 < 3V and KEYLATCH = OFF) the IC consumes only a low current, IK30. Any peaks on the supply voltage (VPulse in Figure 5-1) will gradually charge the blocking capacitor (C1). D1 prevents the capacitor from being discharged via the power supply and the very small quiescent current via the IC can also be neglected. This means that during long periods of Standby mode, the IC's supply voltage could increase continuously until finally the maximum supply voltage limit would be exceeded and the IC could be damaged. ATA6264 therefore features a discharger circuit which avoids such unwanted effects. If VK30 exceeds a threshold value of approximately 26.8V, the blocking capacitor is discharged via an integrated resistor until VK30 again falls below the threshold. Figure 5-1. Discharger Circuit
K30 D1
8 k 26.8V
C1
VBatt
VPulse
5.2
Initial Programming of the ATA6264
The ATA6264 supports different output voltages at the VSAT, VPERI and the VCORE regulators. In addition, different modes at the ISO9141 interfaces can be adjusted at the initial programming (IP). The memory cells are one-time programmable (OTP) and cannot be changed after the IP (default values are "0"). In general, the IP is done after mounting the ATA6264 on the PCB with an in-circuit tester. The programming voltage of 11.7V has to be applied on pin VSAT. It is also possible to use the VSAT regulator as the programming voltage because VSAT is programmed to 11.7V (0.5V) as long as the Test mode is entered and the lock bit is not set. To ensure proper programming of the ATA6264, at least a 10-F electrolytic cap and a 100-nF ceramic cap have to be applied at pin VSAT.
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The following settings can be made at the initial programming:
MSBit VR1
VR2
VR3
VR4
EXT
ISO/LIN
Parity
LSBit Lock bit
Table 5-2.
VR1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Initial Programming Settings
VR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VR3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VR4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCORE 1.88V 1.88V 1.88V 2.5V 2.5V 2.5V 1.88V 1.88V 1.88V 2.5V 2.5V 2.5V 5V 5V 5V VPERI 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 5V 5V 5V 5V 5V VSAT 7.8V 9.1V 10.4V 7.8V 9.1V 10.4V 7.8V 9.1V 10.4V 7.8V 9.1V 10.4V 7.8V 9.1V 10.4V All regulators deactivated (default)
Set to 0 EXT No external transistor at VPERI (default)
Set to 1 External transistor at VPERI applied
Set to 0 ISO/LIN ISO9141 mode is activated at K1 (default)
Set to 1 LIN mode is activated at K1
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The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock bit is not set, the programming will not be executed. Figure 5-2. Programming Sequence
Contact pins RESQ, RESQ2 TxD1, TxD2, SSQ, MOSI, SCLK, VPERI, K15, K30
Apply 12V at K15, K30 and5V at VPERI
Set RESQ and TxD1 to GND and RESQ2 and TxD2 to 5V
Transmit 5A5A(h) via SPI to Enable Testmode
Wait until VSAT = 11.7V
Transmit IP command A9xx(h) via SPI to configure ATA6264
Wait 1 ms
Remove all voltages and pinloads to get out of Test mode
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5.3
Start-up and Power-down Procedure
The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is connected to the ignition key line K15. In order to detect an interruption on one of these pins correctly, resistors are implemented at these pins. Normally, the main supply pin of ATA6264 is pin K30. In the case of a missing or a too-low voltage at pin K30, the whole IC is supplied from the backup power supply capacitor hooked up to pin EVZ.
Figure 5-3.
Block Diagram Start-up and Power-down Procedure
K15 K15GOOD VK15 = 3V to 4.15V (40 mV to 175mV Hysteresis) Serial interface (KEY - LATCH) CP IREF lost signal VK30 Comp EVZEN VEVZ driver IP EVZ VEVZ = 7.5V to 9V (ON) VEVZ = 5.5V to 6.2V (OFF) VCP EVZGOOD Comp VSAT driver GEVZ Comp K30
VEVZ
VCP
K30GOOD VK30 = 3.85V to 5V (50 mV to 150 mV Hysteresis)
CORESWAP VK30 = 6.1V to 8.1V (ON) (0.5V to 1V Hysteresis) Comp 5V
VEVZ
SVSAT
VSAT VEVZ VSATGOOD VSAT = 6.77V to 7.2V (200 mV to 500 mV Hysteresis) Comp Power sequencing VPERI driver SVPER VPERI K30 VCP
VVSAT
VVPERI
IP
VCORE driver VCP CORE_EN VPERI = 1.25V to 1.7V (50 mV to 150 mV Hysteresis) Comp
SVCORE
VCORE VCore driver EVZ
VVCORE
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Depending on the initial programming of the ATA6264, the start-up procedure takes place in different phases. 5.3.1 Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via the serial interface. Phase2: If VEVZ is larger than 7.5V to 9V the VSAT regulator starts operating and the VCORE regulator will be enabled. Phase3: After V VSAT has reached 6.77V to 7.2V, the VPERI regulator starts working. The VCORE regulator starts operating depending on the charge pump voltage. 5.3.2 The Power-down Procedure Takes Place in Different Phases Phase1: If the ignition key is switched off, K15 voltage will vanish at pin K15. If the serial interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in Permanent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ. Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops to low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on mode, the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage. If the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off. Depending on the charge-pump voltage, the VCORE regulator stops working. Phase3: When the voltage at the EVZ capacitor gets to be lower than 5.5V to 6.2V, VSAT is switched off.
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Figure 5-4.
Start-Up and Power-Down Procedure if VVCORE Programmed to Be 5V or 2.5V
VK30
t
VK15
3V to 4.15V 3V to 4.15V
t
VGEVZ
Threshold to enable VCORE regulator
t
VEVZ
7.5V to 9V
too low EVZ voltage VSAT goes into On Mode charge pump deactivated
5.5V to 6.2V
Threshold to start VCORE regulator
t
VVSAT
6.77V to 7.2V 7V to 6.27V
t
VVPERI
VVCORE
t
t
5.3.3
Start-up Procedure if VVCORE Programmed to Be 1.88V Phase1: After switching on the ignition key, the K15 voltage will appear at pin K15. If, in addition, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set by the serial interface. Phase2: If VEVZ is larger than 7.5V to 9V, the VSAT regulator starts operating. Phase3: After VVSAT has reached 6.77V to 7.2V, the VPERI regulator starts working. Phase4: If VVPERI is higher than 1.25V to 1.7V, the VCORE regulator will be enabled.
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5.3.4 The Power-down Procedure for VVCORE is Programmed to be 1.88V Phase1: If the ignition key is switched off, the K15 voltage will vanish at pin K15. If the serial interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Permanent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ. Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops too low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on mode, the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage. If the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off. Depending on the charge-pump voltage, the VCORE regulator stops working. The power sequencing function for the VPERI regulator is still active and guarantees a maximum voltage difference between VPERI and VCORE of 2.8V Phase3: After VVPERI becomes lower than 1.1V to 1.55V, the VCORE regulator has to stop working. Phase4: When the voltage at the EVZ capacitor is lower than 5.5V to 6.2V, VSAT is switched off. Figure 5-5. Start-up and Power-down Procedure if VVCORE Programmed to Be 1.88V
VK30
t
VK15
3V to 4.15V 3V to 4.15V
t
VGEVZ
t
VEVZ
7.5V to 9V
too low EVZ voltage VSAT goes into On Mode charge pump deactivated
5.5V to 6.2V
t
VVSAT
6.77V to 7.2V 7V to 6.27V
t
VVPERI
1.25V to 1.7V 1.1V to 1.55V
VVCORE
t
t
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6. Power Supply Sequencing
(Only active when initial programming sets VVCORE = 1.88V and VVPERI = 3.3V) In order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented. The ATA6264 ensures that the voltage difference VPERI - VCORE will not exceed 2.8V. The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if the VCORE regulator does not start to work, the difference may rise above the 2.8V threshold. In this case, the VPERI regulator is switched off before reaching this level and switched on again if the voltage difference drops below a hysteresis value. Figure 6-1.
VVPERI
Example for Incorrect Ramp Up
3.3V
t
VVCORE 1.88V Not allowed area: VVPERI - VVCORE > 2.8V
t
Necessary for operation: VEVZ = 0V to 40V, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VK30, VVSAT, VVPERI and VVCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 6-1.
Electrical Characteristics - Power Supply Sequencing
Test Conditions Pin VPERI, VCORE VPERI, VCORE Symbol VVPERI - VVCORE VVPERI - VVCORE
VHYS
No. Parameters 5.1 5.2a 5.2b Maximum voltage difference VVPERI - VVCORE Voltage level VVPERI - VVCORE to switch off VPERI regulator Hysteresis for VVPERI - VVCORE to enable VPERI regulator
Min 0 2.3
Typ.
Max. 2.8 2.8 100
Unit V V mV
Type* A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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ATA6264 [Preliminary]
Figure 6-2. Block Diagram Power Supply Sequencing
K15 K15GOOD VK15 = 3V to 4.15V (40 mV to 175mV Hysteresis) Serial interface (KEY - LATCH) CP IREF lost signal VK30 Comp EVZEN VEVZ driver GEVZ Comp K30
VEVZ
VCP
K30GOOD VK30 = 3.85V to 5V (50 mV to 150 mV Hysteresis)
CORESWAP VK30 = 6.1V to 8.1V (ON) (0.5V to 1V Hysteresis) Comp 5V IP
EVZ VEVZ = 7.5V to 9V (ON) VEVZ = 5.5V to 6.2V (OFF) VCP EVZGOOD Comp VSAT driver
VEVZ
SVSAT
VSAT VSATGOOD VSAT = 6.77V to 7.2V (200 mV to 500 mV Hysteresis) Comp IP VPERI driver SVPER VPERI VEVZ
VVSAT
VVPERI
Delta < 2.8V
VCORE - Regulator
SVCORE
VCORE
VVCORE
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4929B-AUTO-01/07
7. Charge Pump
To supply the VSAT and VCORE drivers, an external charge pump is provided. Both FETs(1) are driven by the high charge pump voltage VCP to ensure that they can be switched to a low-ohmic state. For correct function of the charge pump, an external capacitor of C = 47 nF has to be connected to pin SVSAT, and another of C = 100 nF to pin CP. A double diode has to be implemented for proper function of the charge pump. An external series resistor is recommended to suppress spikes during switching of the SVSAT. The CP block is supplied by EVZ and VSAT voltage and starts to operate as soon as the thresholds for VK15, K30 and EVZ are achieved. An additional start-up circuitry is implemented to support the VSAT driver during the start-up phase, thus enabling a reliable system startup. The charge pump has an output CP-OUT to supply the external circuitry, and can be switched via the SPI. It is capable of 250 A. Figure 7-1. Block Diagram Charge Pump
External circuit
CP-Out Status register REF
CP
VSAT REF
SVSAT Status register
Serial interface
I = 1.4 mA
EVZ
Note:
1. Connected to the drivers (see Figure 5-3)
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Necessary for operation: VEVZ = 5.5V to 40V or VK30 = 5.5V to 40V, VK15 > 3V, VVINT = 3.7V to 5.47V Operating conditions of all other supply pins: VVSAT, VVPERI and VVCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 7-1.
Electrical Characteristics - Charge Pump
Test Conditions CP off, supply of internal circuitry Pin CP Symbol ICP td ICP-OUT VDiff td 0 Min 0 Typ. Max. 50 Unit A Type* A
No. Parameters 6.11 Supply current at pin CP Time between wrong CP-OUT 6.12 voltage and valid data in status register 6.13 6.14 Current limitation at pin CP-OUT Voltage difference VCP - VEVZ for detecting wrong CP
CP-OUT
0
50
s
A
CP-OUT Note: Threshold is in the range of 5V to 7V CP
-0.8
-4.2 5
mA V
A A
Time between wrong CP 6.15 voltage and valid data in status register Voltage difference VCP-OUT - 6.16 VEVZ for detecting wrong CP-OUT Note: Threshold is in the range of 5V to 7V VEVZ = 5.5V to 40V, VK30 < VEVZ ICP + ICP_Out = -100 A (current consumption of VSAT and VCORE have to be added) VEVZ = 5.5V to 40V, VK30 < VEVZ ICP + ICP_Out = -100 A (current consumption of VSAT and VCORE have to be added)
CP
50
s
A
CP-OUT
VDiff
5
V
A
6.17 Voltage at pin CP
CP
VCP
VEVZ + 7
VEVZ + 11
V
A
6.18 Voltage at pin CP
CP
VCP
VK30 + 7
VK30 + 11
V
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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8. GKEY Function
The GKEY function is used to enable or disable the ECU via a powerless signal. If the voltage at pin K15 is larger than 3V to 4.15V, the charge pump and the EVZ regulator (for correct EVZ function, the K30 pin has to be connected to the battery) will start operating. If the K15 pin is open, an internal pull-down resistor of approximately 220 k discharges the pin. A logical connection between the voltage at the K15 pin, a serial-interface-driven latch command, and the K30 voltage determines the EVZ Enable signal. In order to achieve the Switch Function of the GKEY function, a transformer has to be used.
Table 8-1.
Overview of the Start-up Conditions
Serial-interfacedriven Latch (Default: "0" = OFF) x
3)
VK30 Low
1) 2) 2)
VK15 x High x
EVZ Regulator Disabled Enabled Enabled
High High Note:
x 1
1. Less than the value shown in number 7.3 of Table 8-2 on page 23 2. Greater than the value shown in number 7.3 of Table 8-2 on page 23 3. Greater than the value shown in number 7.1 of Table 8-2 on page 23
Figure 8-1.
Application With Low-current Switch (GKEY Function Used)
VBATT
K15
GKEYLogic
K30
GEVZ EVZ OCEVZ GNDB
EVZ FBEVZ
VEVZ
COMEVZO
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Figure 8-2. Application With High Current Switch (GKEY Function Not Used)
VBATT
K15
GKEYLogic
K30
GEVZ EVZ OCEVZ GNDB
EVZ FBEVZ
VEVZ
COMEVZO
Necessary for operation: VK15 = 3V to 40V, VK30 = 3.85V to 40V Operating conditions of all other supply pins: VEVZ, VSAT, VPERI and VCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 8-2.
Electrical Characteristics - GKEY Function
Test Conditions VK15 increasing, VK30 > 5V Pin K15 K15 VK30 increasing, VK15 > 4.15V K30 K30 K15 K30 0V VK15 40V, AMUX measurement EVZ active K15 Symbol VK15 VK15 VK30 VK30 RK15 RK30 IK15 Min 3 40 3.85 50 70 320 0 Typ. Max. 4.15 175 5 150 365 1700 1.1 Unit V mV V mV k k mA Type* A A A A A A A
No. Parameters 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Voltage level at K15 to enable the EVZ regulator Hysteresis at K15 to disable the EVZ regulator Voltage level at K30 to enable the EVZ regulator Hysteresis at K30 to disable the EVZ regulator Pull-down resistor at K15 Pull-down resistor at K30 Current at K15
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. EVZ Step-up Regulator
A boost converter generates the supply voltage for energy reserve and firing capacitors in the system. Using a voltage divider at pin FBEVZ, this voltage can be adjusted between 15V and 40V. Thus, high-voltage charged capacitors will be used to supply the whole system during the stand-alone time (for example, broken K30 line after a crash). The step-up regulator has to start running as soon as a certain threshold voltage at the K15 pin is exceeded. The regulator has to stop running again if the voltage at the K15 pin falls below a voltage level (or voltage at pin K30 is missing, see Section 5.3 "Start-up and Power-down Procedure" on page 14). An inductor is PWM-switched by an external n-channel power FET with a fixed frequency of 100 kHz. A driver stage for the external FET is integrated into the ATA6264. The current limitation of the external FET is implemented by using an external resistor in series between the source connection of the external FET and GND, sensing the voltage drop at this resistor via the pins OCEVZ and GNDA. The reference section provides a reference voltage of 1.24V for the regulation loop. An error amplifier compares the reference voltage with the feedback signal, which is provided either from two different serial-interface-programmable internal dividers (VEVZ1 = 22V, VEVZ2 = 31.5V) or an external voltage divider network (VEVZExt). These dividers determine the output voltage EVZ. Figure 9-1. EVZ Regulator With External Divider
K30 Max. duty-cycle Bandgap reference Low battery Sawtooth oscillator L
RVZ1
+ Error amp.
+ PWM comp.
Logic and driver
GEVZ
OCEVZ Overcurrent
C+
EVZ overvoltage GNDA
RVZ2
SPI
SPI
SPI
EVZ FBEVZ
COMEVZO
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Figure 9-2. EVZ Regulator With Internal Divider
K30 Max. duty-cycle Bandgap reference Low battery Sawtooth oscillator L
+ Error amp.
+ PWM comp.
Logic and driver
GEVZ
OCEVZ Overcurrent
C+
EVZ overvoltage GNDA
SPI
SPI
SPI
EVZ FBEVZ
COMEVZO
A draft formula for calculating the EVZ voltage, which is programmed by the external voltage divider network at pin FBEVZ, is:
R VZ1 + R VZ2 V EVZ = V REF x ------------------------------R VZ2
The pins EVZ and FBEVZ have to be shorted in applications without an external divider in order to ensure a safe operation of the ATA6264 in the case of an EVZ-pin fault. If the voltage at pin FBEVZ is larger than the voltage at pin EVZ, the ATA6264 switches the feedback path automatically to pin FBEVZ. The remaining voltage at FBEVZ causes the regulator to switch off. The output of the error amplifier is compared with a periodic linear ramp of a saw-tooth generator by the PWM comparator. A logic signal with variable pulse width is generated, which controls the PWM frequency of the external FET. A maximum duty cycle is determined by the duration of the falling ramp of the saw-tooth oscillator. The saw-tooth generator is controlled by the internal 100-kHz oscillator.
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4929B-AUTO-01/07
Figure 9-3.
Functional Principle of the EVZ Regulator
Sawtooth
t
Error amp. output = f (VEVZ) on off
PWM output
t
The output transistor conduction is suppressed immediately if the current through the power FET exceeds a certain level, determined by the voltage drop across an external resistor in the range of 0.2. The ATA6264 itself will see a voltage at the OCEVZ pin. If this voltage exceeds typically 0.5V, the output transistor conduction has to be suppressed. The external FET also has to be switched off if a low battery voltage at K30 or overvoltage on pin EVZ is detected. Multiple output pulses at pin GEVZ during one oscillator period are suppressed by internal logic. In the default state - for example, before the minimum input voltage for starting the regulator has been reached - the external transistor is switched off. During startup, the voltage on pin EVZ is too low and the PWM comparator requires a duty cycle of more than 90%. Due to an increasing inductance current, after several periods the overcurrent sensor becomes active and reduces the maximum duty cycle to improve magnetic energy transfer. Figure 9-4.
Output current
Output Current During Start-up
Current limit
t
A capacitance of 10 mF or more may be applied at pin EVZ. The equivalent series resistance (ESR) should have a value of less than 0.5. After power-on, the default state of the internal dividers should always be the low EVZ voltage divider. The voltage at pin GNDA is compared with the voltage at pin GNDD, and if GNDA is not connected, bit b6 of the APACE status register is set. Pin GNDB is also compared with pin GNDD. Pin GNDB not being connected will also result in bit b6 being set, and, additionally, in the EVZ regulator being switched off.
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Necessary for operation: VK15 = 3V to 40V, VK30 = 5V to 40V, CGEVZ = 200 pF to 2 nF, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VSAT, VPERI and VCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 9-1.
Electrical Characteristics - EVZ Step-up Regulator
Test Conditions VK30 8V or VEVZ 8V (after startup) 4V < VK30 < 8V or 4V < VEVZ < 8V (after startup) See number 7.1 of Table 8-2 on page 23 See number 7.2 of Table 8-2 on page 23 See number 7.3 of Table 8-2 on page 23 See number 7.4 of Table 8-2 on page 23 VK30 3.85V to 5V (ON threshold) VK30 7V VGEVZ 5V VGEVZ = 5V VGEVZ = 10V GEVZ GEVZ VGEVZ VGEVZ IGEVZ QGEVZ QGEVZ RGEVZ RGEVZ VOCEVZ DGEVZ 0.475 VK30 - 0.5V 6 VK30 10 V V Pin GEVZ Symbol fGEVZ fGEVZ Min -5% Typ. 100 Max. +5% Unit kHz Type* A
No. Parameters 8.1 Switching frequency
8.2
Switching frequency Voltage level at K15 to start the EVZ regulator Hysteresis at K15 to stop the EVZ regulator Voltage level at K30 to start the EVZ regulator Hysteresis at K30 to stop the EVZ regulator Voltage at pin GEVZ to switch through the external driver Voltage at pin GEVZ to switch through the external driver Driving current at pin GEVZ to switch through the external driver Gate charge delivered to the external FET Gate charge delivered to the external FET RDson of dynamic sinking transistor at GEVZ Voltage between pins OCEVZ and GND to detect overcurrent
GEVZ
-10%
100
+10%
kHz
A
8.3 8.4 8.5 8.6 8.7 8.8
A A A A A A
8.9
GEVZ
-600
-80
mA
A
8.10 8.11
GEVZ GEVZ GEVZ GEVZ OCEVZ
10 20 20 50 28 0.525
nC nC k V
D D A A A
8.12 Pull-down resistor at pin GEVZ 8.13 8.15
8.16 Maximum switch duty cycle
VK30 8V or VEVZ 8V (after startup) VEVZ 8V 4V < VK30 < 8V or 4V < VEVZ < 8V (after startup)
GEVZ
87.5
90
92.5
%
A
8.17 Maximum switch duty cycle 8.18 Minimum switch duty cycle
GEVZ GEVZ VEVZ
DGEVZ DGEVZ VEVZ
75
90
92.5 0
% % V
A A A
Overvoltage at pin EVZ to switch VEVZExt programmed 8.19 (via external divider) off the regulator
40.5
46.2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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4929B-AUTO-01/07
Table 9-1.
Electrical Characteristics (Continued)- EVZ Step-up Regulator
Test Conditions Pin VEVZ VEVZ Symbol VEVZ VEVZ Min 25 35 Typ. Max. 28.5 39.5 Unit V V Type* A A
No. Parameters 8.19a 8.19b
Overvoltage at pin EVZ to switch VEVZ1 programmed off the regulator Overvoltage at pin EVZ to switch VEVZ2 programmed off the regulator Time between reaching overvoltage and reaching 90% of the value at numbers 8.7 and 8.8 of Table 9-1 on page 27 Time between reaching overcurrent and reaching 90% of the value at numbers 8.7 and 8.8 of Table 9-1 on page 27
8.20 Overvoltage switch-off time
GEVZ
toffov
200
ns
D
8.21 Overcurrent switch-off time
GEVZ
toffoc
500
ns
A
8.22
Switch-on delay time for the boost converter output stage Time between 0.5V and Switch-on rise time for the boost 4.5V at GEVZ, converter output stage CGEVZ = 2 nF Switch-off delay time for the boost converter output stage Switch-off fall time for the boost converter output stage Time between 4.5V and 0.5V at GEVZ, CGEVZ = 2 nF
GEVZ
tdon tron tdoff tfoff IOCEVZ IOCEVZ VFBEVZ VFBEVZ VEVZ1
50
250
ns
A
8.23
GEVZ
10
200
ns
A
8.24
GEVZ
50
150
ns
A
8.25
GEVZ OCEVZ FBEVZ
10 -10 -10 1.20 1.24 1.24
100 +10 +10
ns A A V
A A A A A
8.26 Leakage current at pin OCEVZ 8.27 Leakage current at pin FBEVZ 8.28 Switch-on threshold via FBEVZ 8.29 Switch-on threshold via FBEVZ Band-gap tolerance included Band-gap tolerance included VEVZ1 programmed, Band-gap tolerance included VEVZ2 programmed, Band-gap tolerance included
FBEVZ FBEVZ
1.28
V
8.30 VEVZ voltage #1 set by SPI VEVZ voltage #2 set by SPI Temperature shutdown activation Hysteresis for reactivation of GEVZ
EVZ
20
23
V
A
8.31
EVZ
VEVZ2 Toff Thys
28.6
33
V
A
8.31a 8.31b
155 5
185 25
C K
B B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Table 9-1. Electrical Characteristics (Continued)- EVZ Step-up Regulator
Test Conditions Pin Symbol Min Typ. Max. Unit Type* No. Parameters Error Amplifier 8.32 8.33 Output current at pin COMEVZO sinking to low Output current at pin COMEVZO driving to high COMEVZO COMEVZO ICOMEVZO ICOMEVZO 0.4 -1000 -10 70 2 ICOMEVZO = 100 A ICOMEVZO = -100 A COMEVZO COMEVZO VCOMEVZO VCOMEVZO 0 VINT - 0.3V 0.2 10 0.2 0.2 VINT 3 -150 +10 mA A mV dB MHz V V A A D D D A A
8.34 Input offset voltage 8.35 DC open-loop gain 8.36 Unity-gain bandwidth 8.37 8.38 Output voltage low on pin COMEVZO Output voltage high on pin COMEVZO
GNDA/GNDB Disconnect 8.40 GNDA lost detection 8.41 Delay for GNDA lost detection 8.42 GNDB lost detection VGNDB - VGNDD VGNDA - VGNDD GNDA GNDA GNDB VGNDA td VGNDB 0.4 50 0.4 V s V A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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10. VSAT Power Supply
A stabilized VSAT supply is realized by a buck converter. An external inductance is PWM-switched with a frequency of 200 kHz via an internal high-side DMOS power transistor. The VSAT power supply is connected to the boost converter output (EVZ), and uses the stored energy of the boost converter capacitor if the voltage at K30 is missing. The regulator uses both current and voltage feedback. The basis for the regulation loop is a temperature-compensated band-gap reference voltage, which is compared with the internally divided output voltage VSAT. The error amplifier output is applied to the inverting input of a comparator, the current feedback is connected with the positive input. The PWM flip-flop (which is set every 5 s by the oscillator) is reset if the current feedback reaches the error amplifier level. In order to adjust the compensation of the regulation loop and therefore improve the behavior in case of load changes in continuous-mode operation, pin COMSATO has to be connected to COMSATI via a compensation network. Because of the fact that current-mode-controlled converters exhibit sub-harmonic oscillations when operating at duty cycles higher than 50%, a slope compensation (which adds an artificial ramp to the comparator) is implemented. If the regulator input voltage at pin EVZ is too low, the regulator switches to a duty cycle of 100% (Permanent-on mode). The VSAT voltage can be programmed via the serial interface to one of three different voltage values during initial programming. Figure 10-1. Functional Principle of the VSAT Regulator
CP
EVZ Slope compensation Bandgap reference COMSATI Current measurement and leading edge blanking
VSAT
+ Error amp.
+ Comp.
OSC
Overcurrent SVSAT
VSAT
SPI OTP
S Q R
Logic and driver
+
Overvoltage
COMSATO
The duration of the output transistor conduction depends on the VSAT level and current feedback. Conduction is suppressed immediately if the current through the output transistor exceeds 850 mA typically. A logic circuit disables, in the case of short spikes, multiple-pulse operation during one oscillating period. If pin VSAT is open (VSAT loss), an internal current source connected to a higher voltage than VSAT acts as pull-up for this pin, to prevent the VSAT voltage from rising up to EVZ. In order to ensure the gate voltage for the output transistor, the driver stage is supplied by the charge pump (pin CP).
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Necessary for operation: VEVZ = 5.5V to 40V, VCP > VEVZ + 7V, VINT = 3.7V to 5.45V Operating conditions of all other supply pins: VK30, VPERI and VCORE are within functional range limits, Tj = -40C to +150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 10-1.
Electrical Characteristics - VSAT Power Supply
Test Conditions Pin EVZ EVZ SVSAT SVSAT VEVZ 8V 5.5V > VEVZ 8V SVSAT SVSAT SVSAT SVSAT Band-gap tolerance included VVSAT2 programmed, Band-gap tolerance included VVSAT3 programmed, Band-gap tolerance included VSAT Symbol VEVZ VEVZ tSVSAT tSVSAT fSVSAT fSVSAT ISVSAT RSVSAT VVSAT1 VVSAT2 -4% 7.8 Min 7.5 5.5 0 0 -5% -10% 0.8 200 200 Typ. Max. 9 6.2 20 5 +5% +10% 1 1 +4% Unit V V s s kHz kHz A V Type* A A A A A A A A A
No. Parameters 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 VEVZ voltage for the buck converter to start running VEVZ voltage for the buck converter to stop Regulator switch-on time via pin EVZ Regulator switch-off time via pin EVZ Regulator switching frequency Output current limit RDson of output transistor Output voltage #1 only at VPERI = 3.3V Output voltage #2
9.5a Regulator switching frequency
9.9
VSAT
-4%
9.1
+4%
V
A
9.10 Output voltage #3
VSAT
VVSAT3
-4%
10.4
+4%
V
A
Time between reaching 0.1 x (VEVZmax - VSVSATmin) 9.11 Output transistor switch-on time and 0.9 x (VEVZmax - VSVSATmin) Time between reaching 0.9 x (VEVZmax - VSVSATmin) 9.12 Output transistor switch-on time and 0.1 x (VEVZmax - VSVSATmin) 9.13 Overvoltage switching off the regulator Time between reaching overvoltage and reaching 90% of VSVSAT maximum under on condition VSAT VVSAT
150
ns
A
150 1.1 x VSATX 0 0.4
ns
A
V
A
9.14 Overvoltage switch-on time
SVSAT
tSVSAToff
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation; sub-harmonics must be prevented 2. The value of the minimum load current must be higher than the internal pull-up current at pin VSAT to ensure proper function of the regulator
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4929B-AUTO-01/07
Table 10-1.
Electrical Characteristics (Continued)- VSAT Power Supply
Test Conditions Time between reaching overcurrent and reaching 90% of VSVSAT maximum under on condition Output transistor off Pin Symbol Min Typ. Max. Unit Type*
No. Parameters
9.15 Overcurrent switch-on time
SVSAT
tSVSAToff ISVSAT
0
0.5
s
A
9.16 Leakage current at pin SVSAT Error Amplifier 9.17 9.18 9.19 Maximum output current at pin COMSATO sinking to low Maximum output current at pin COMSATO sourcing to high Input impedance at pin COMSATI
SVSAT
-10
+10
A
A
COMSATO COMSATO COMSATI
ICOMSATO ICOMSATO RCOMSATI
200 -165 9 -10 70 2
3000 -85 23 +10
A A k mV dB MHz
A A A D D D A A D D D
9.20 Input offset voltage 9.21 DC open-loop gain 9.22 Unity-gain bandwidth 9.23 Output voltage low 9.24 Output voltage high 9.25 Leading-edge blanking time 9.26 Slope of artificial ramp for slope compensation ICOMSATO = 165 A ICOMSATO = -85 A COMSATO COMSATO VCOMSATO VCOMSATO tblank dV/dt ILoad
0 VVINT - 0.6V 150 150(1) 0
0.3 VVINT 200 240(1) 1.5
V V ns mV/s mA
9.27 VSAT loss detection threshold(2) Notes:
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Depending on implementation of slope compensation; sub-harmonics must be prevented 2. The value of the minimum load current must be higher than the internal pull-up current at pin VSAT to ensure proper function of the regulator
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11. VPERI Power Supply
With the VPERI regulator a stabilized and ripple-free voltage is generated out of the VSAT supply voltage. This voltage is intended to be used for sensitive components, for example, sensors or reference inputs of A/D converters from microcontrollers. For this reason, a linear regulator is implemented to guarantee high ripple rejection and a precise voltage. The regulator output is short-circuit protected by an overcurrent protection. If pin VPERI is disconnected, the regulator is switched off and RESQ/RESQ2 are set to low. Figure 11-1. Functional Principle of the VPeripheral Regulator
VSAT
VSAT
SVPERI
VPeripheral Linear regulator
VPERI
VPeripheral
If a higher current capability of the regulator is requested or if the power dissipation of the linear regulator is too high, an external transistor can boost the regulator. Figure 11-2. Functional Principle of the VPERI Regulator With External Boost Transistor
VSAT
VSAT
SVPERI
VPeripheral Linear regulator
VPERI
VPeripheral
The VPERI voltage can be programmed via the serial interface to one of two different voltage values during initial programming.
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4929B-AUTO-01/07
Necessary for operation: VSAT > 7.5V, VINT = 3.7V to 5.47V, VCORE < VPERI + 0.3V Operating conditions of all other supply pins: VK30, VEVZ and VCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 11-1.
Electrical Characteristics - VPERI Power Supply
Test Conditions Pin VSAT VSAT VVPERI1 programmed, band-gap tolerance included VVPERI2 programmed, band-gap tolerance included VVSAT = 7.5V to 12.5V VVSAT = 8V to 12.5V IPERI = -1 mA to -100 mA (IPERI is constant during measurement) VSAT = 8V to 12.5V (VVSAT is constant during measurement) IPERI = -1 mA to -100 mA IPERI = -100 mA, f = 100 kHz - 20 MHz, CPERI = 47 F + 100 nF (ceramic) Symbol VVSAT VVSAT VVPERI Min 6.77 0.2 Typ. Max. 7.2 0.5 Unit V V Type* A A
No. Parameters Voltage level at VSAT to enable 10.1 VPERI regulator 10.2 Hysteresis at VSAT to disable VPERI regulator
10.3 Output voltage #1
VPERI
-3.6%
5
+4%
V
A
10.4 Output voltage #2 10.5 Output current 10.6 Short-circuit current
VPERI VPERI VPERI
VVPERI IVPERI IVPERI VVPERI
-4% -100 -200
3.3
+3%
V mA
A A A
-110
mA
10.7 Line regulation
VPERI
-10
+10
mV
A
10.8 Load regulation
VPERI
VVPERI
-10
+10
mV
A
10.10 Supply voltage rejection
40
dB
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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ATA6264 [Preliminary]
12. VCORE Power Supply
The voltage of the VCORE regulator is generated out of the K30 voltage using a step-down regulator as long as the K30 voltage is available. During times when K30 is not present (power-down or stand-alone time), the VCORE regulator is supplied out of VEVZ. Depending on the initial programming, the supply switch signal is derived from the CORESWAP comparator or the EVZEN comparator. The VCORE voltage can be programmed via the serial interface to 3 different voltage values during initial programming. In the case of short spikes, a logic circuit disables multiple-pulse operation during one oscillating period. The regulator uses both current and voltage feedback. In the following cases, the output transistor of the regulator is switched off at once and may be switched on again with the beginning of the next clock period: 1. If the current through the transistor exceeds the output current limit value, the transistor is switched off immediately. 2. If overvoltage is detected at the pin VCORE, the transistor is switched off immediately. 3. If the feedback voltage at the pin VCORE is missing (disconnected pin), the regulator is switched off. Figure 12-1. Functional Principle of the VCORE Regulator
Controlsignal K30/EVZ
K30 Slope compensation Current measurement and leading edge blanking
OSC VCORE Bandgap reference COMCOI S
Overcurrent
VCORE
SVCORE Q Logic and driver
+ Error amp.
+ Comp.
R
+
Overvoltage
SPI OTP Slope compensation COMCOO CP Current measurement and leading edge blanking
EVZ
In order to trim the compensation of the regulation loop and to improve the behavior at load changes, pin COMCOO has to be connected to COMCOI via a compensation network. Because of the fact that current-mode-controlled converters exhibit sub-harmonic oscillations when operating at duty cycles larger than 50%, a slope compensation (which adds an artificial ramp to the comparator) is implemented. If the regulator input voltage at pin EVZ or pin K30 is too low, the regulator switches to a duty cycle of 100% (Permanent-on mode). Backward feeding of EVZ and K30 is avoided. In order to ensure the gate voltage for the output transistors of the regulator, the driver stages are supplied by the charge pump (pin CP).
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4929B-AUTO-01/07
Necessary for operation: VEVZ = 5.5V to 40V or VK30 = 5.5V to 40V, VCP > VEVZ + 7V or VCP > VK30 + 7V, VPERI > VCORE - 0.3V, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VSAT is within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8. Table 12-1.
No. 11.1
Electrical Characteristics - VCORE Power Supply
Test Conditions Pin EVZ Symbol VEVZ VVPERI VEVZ VHYS tSVCORE tSVCORE fSVCORE ISVCORE RSVCORE VVCORE1 -4% 5.0 0.7 0.9 1.2 +4% A V Min 7.5 Typ. Max. 9 Unit V Type* A
Parameters
VEVZ voltage for the VCORE Initial programming: regulator to start running VVCORE = 5V or 2.5V Initial programming: VVCORE = 1.88V
VVPERI voltage for the 11.1a VCORE regulator to start running 11.2
VPERI
1.25
1.7
V
A
VEVZ voltage for the VCORE Initial programming: regulator to stop running VVCORE = 5V or 2.5V Initial programming: VVCORE = 1.88V
EVZ
5.5
6.2
V
A
Hysteresis at VPERI for the 11.2a VCORE regulator to stop running 11.3 11.4 11.5 11.6 11.7 11.8 Switch-on time via pin EVZ Switch-off time via pin EVZ Regulator switching frequency Output current limit RDson of output transistor Output voltage #1
VPERI SVCORE SVCORE
50 0 0
150 20 10
mV s s
A A A A A A A
See numbers 8.1 and 8.2 of Table 9-1 on page 27
SVCORE SVCORE SVCORE
VVCORE1 programmed, band-gap tolerance included VVCORE2 programmed, band-gap tolerance included VVCORE3 programmed, band-gap tolerance included Time between reaching 0.1 x (VK30max - VVCOREmin) and 0.9 x (VK30max - VVCOREmin) or 0.1 x (VEVZmax - VVCOREmin) and 0.9 x (VEVZmax - VVCOREmin)
VCORE
11.9
Output voltage #2
VCORE
VVCORE2
-4%
2.5
+4%
V
A
11.10 Output voltage #3
VCORE
VVCORE3
-4%
1.88
+4%
V
A
11.11
Output transistor switch-on time
SVORE
tSVCOREon
150
ns
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented. 2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator.
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Table 12-1.
No.
Electrical Characteristics (Continued)- VCORE Power Supply
Test Conditions Time between reaching 0.1 x (VK30max - VVCOREmin) and 0.9 x (VK30max - VVCOREmin) or 0.1 x (VEVZmax - VVCOREmin) and 0.9 x (VEVZmax - VVCOREmin) Pin Symbol Min Typ. Max. Unit Type*
Parameters
11.12
Output transistor switch-off time
SVCORE
tSVCOREoff
150
ns
A
Overvoltage at pin VCORE See numbers 14.6 and for switching off the regulator 11.13 14.6a of Table 15-2 on and setting pin RESQ to low page 45 (VCORE is set to 5V) Overvoltage at pin VCORE See numbers 14.7 and for switching off the regulator 11.13a 14.7a of Table 15-2 on and setting pin RESQ to low page 45 (VCORE is set to 2.5V) Overvoltage at pin VCORE See numbers 14.8 and for switching off the regulator 11.13b 14.8a of Table 15-2 on and setting pin RESQ to low page 45 (VCORE is set to 1.8V) Time between reaching overvoltage and reaching 90% of VSCORE maximum under on condition Time between reaching overcurrent and reaching 90% of VSCORE maximum under on condition Output transistor off
11.14 Overvoltage switch-off time
SVORE
tSVCOREoff
0
0.4
s
A
11.15 Overcurrent switch-off time
SVCORE
tSVCOREoff
0
0.5
s
A
11.16
Leakage current at pin SVCORE Maximum output current at pin COMCOO sinking to low
SVCORE
ISVCORE
-10
10
A
A
Error Amplifier 11.17 COMCOO ICOMCOO ICOMCOO RCOMCOI 200 3000 A A
Maximum output current at 11.18 pin COMCOO sourcing to high 11.19 Input impedance at pin COMCOI VCORE = 1.88V VCORE = 2.5V/5V
COMCOO
-165 7.5 13 -10 70 2
-85 18 27 10
A k k mV dB MHz
A
COMCOI
A D D D A A
11.20 Input offset voltage 11.21 DC open loop gain 11.22 Unity-gain bandwidth Output voltage low at pin 11.23 COMCOO 11.24 Output voltage high at pin COMCOO ICOMCOO = 165 A ICOMCOO = -85 A COMSATO COMSATO VCOMSATO VCOMSATO
0 VINT - 0.6
0.3 VINT
V V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented. 2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator.
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4929B-AUTO-01/07
Table 12-1.
No.
Electrical Characteristics (Continued)- VCORE Power Supply
Test Conditions Pin Symbol tblank dV/dt Min 150 80(1) Typ. Max. 200 150(1) Unit ns mV/s Type* D D
Parameters
11.25 Leading-edge blanking time Slope of artificial ramp for 11.26 slope compensation Voltage level at K30 to switch VK30 increasing VCORE supply from EVZ to See number 7.3 of Table 11.27 K30 (VVCORE = 1.8V or 2.5V 8-2 on page 23 programmed) Hysteresis at K30 to switch VCORE supply from K30 to 11.28 EVZ (VVCORE = 1.8V or 2.5V programmed) VK30 decreasing See number 7.4 of Table 8-2 on page 23
A
A
Voltage level at K30 to switch VCORE supply from EVZ to 11.29 VK30 increasing K30 (VVCORE = 5V programmed) Hysteresis at K30 to switch VCORE supply from K30 to 11.30 EVZ (VVCORE = 5V programmed) Time to switch VCORE 11.31 supply from EVZ to K30 or K30 to EVZ 11.32 VCORE loss-detection threshold(2)
K30
VK30
6.1
8.1
V
A
VK30 decreasing
K30
VK30
0.5
1
V
A
SVCORE
tswitch ILoad
0
7.6
s
D
VCORE
0
1
mA
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented. 2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator.
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13. USP Comparator for General Purpose
The USP comparator is used for general purposes, for example, low battery detection. An external resistive voltage divider provides the input signal for pin USP. A missing USP connection or VUSP < 2.44V sets the status register bit b7 to low. During normal operation (VUSP > 2.44V) the status register bit b7 stays high. Figure 13-1. Functional Principle of the USP Comparator
to AMUX USP
+ 2.44V
Status register
GNDA
Necessary for operation: VEVZ = 5.5V to 40V, VPERI > reset threshold, VCORE > reset threshold, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VSAT and VK30 are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 13-1.
Electrical Characteristics - USP Comparator for General Purpose
Test Conditions VUSP = 2.44V VUSP = 0 to 40V Trigger voltage for status register bit 7= high with increasing VUSP Pin USP USP USP Symbol IUSP IUSP VUSP tdeglitch 20 Min -2.5 -2.5 2.44 5% 60 Typ. Max. +2.5 +2.5 Unit A A V s Type* A A A D
No. Parameters 12.1 Input current at pin USP 12.2 Input current at pin USP 12.3 Threshold voltage at pin USP 12.4 De-glitching time
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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14. Reference Voltage and Reference Current Generation
The pin IREF is an output derived directly from the chip's internal reference voltage. This reference source is a band gap. All internally used precise voltages are derived from this band-gap voltage. At pin IREF a reference resistor of 12.4 k has to be applied, providing a reference current. All internally used precise currents are derived from this current. In case of a missing resistor at IREF, the regulators will stop. The power-sequencing block still operates as specified. A defect of the band-gap reference source can be detected by a microcontroller by comparing the voltage at IREF with the voltage at pin VINT (Internal 5V supply), because VVINT is derived from a different band gap.
Table 14-1.
State 1 2 3 4 5 6 7 8
Truth Table for VINT
VEVZ 0 0 0 VEVZ < VK30 VEVZ > 5.5V VEVZ > 5.5V VEVZ > 5.5V VEVZ > VK30 VVINT OFF OFF OFF ON (Supply: K30) ON (Supply: EVZ) - only valid if VINT was already enabled via state #4 ON (Supply: EVZ) - only valid if VINT was already enabled via state #4 ON (Supply: EVZ) - only valid if VINT was already enabled via state #4 ON (Supply: K30)
K30GOOD K15GOOD (VK30 > 4.2V to 5V) (VK15 > 3V to 4V) Low High Low High Low High Low High Low Low High High Low Low High High
Necessary for operation: VEVZ = 5.5V to 40V or VK30 = 3.85V to 40V Operating conditions of all other supply pins: VSAT, VPERI and VCORE are within functional range limits, Tj = -40C to +150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 14-2.
Electrical Characteristics - Reference Voltage and Reference Current Generation
Test Conditions Pin IREF IREF VK30 > VEVZ VK30 = VK30GOOD to 5V VK30 > VEVZ, VK30 = 5V to 6V VK30 > VEVZ, VK30 = 6V VEVZ > VK30 VK30 = 0V, VEVZ > 6V VINT VINT IREF IREF Symbol VIREF IIREF VVINT VVINT VIREF VIREF 3.35 3.7 4.2 4.2 Min Typ. 1.24 4% 100 4% 5.47 5.47 5.47 5.47 Max. Unit V A V V V V Type* A A A A A A
No. Parameters 13.1 Reference voltage VIREF 13.2 Reference current IREF 13.3a Voltage at VINT 13.3b Voltage at VINT 13.3c Voltage at VINT 13.3d Voltage at VINT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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15. Reset Function (Pin RESQ and Pin RESQ2)
Pins RESQ and RESQ2 are low-active digital outputs of the ATA6264, which provide a digital "low" signal in the case of a missing or incorrect watchdog transmission or in the case of improper VEVZ, VPERI or VCORE voltage. The voltage at pin RESQ depends on the proper voltages at pins EVZ, VCORE, and VPERI. The RESQ signal will be set to high after a 16-ms delay as soon as the VCORE reset threshold and the VPERI reset threshold and the EVZ reset threshold (signal EVZGOOD = high) have been reached. If the watchdog circuitry does not detect a valid watchdog trigger, the RESQ signal is set to low again. If the watchdog was triggered successfully, RESQ stays high and RESQ2 is also set to high. In the case that an overvoltage at VCORE or VPERI is detected, the voltages at pins RESQ and RESQ2 are set to low. Figure 15-1. Functional Principle of RESQ, RESQ2
VEVZ
VEVZ is above reset threshold
VCORE
VCORE is above reset threshold and below overvoltage RESQ
VPERI
VPERI is above reset threshold and below overvoltage
RESQ2
WD-logic
Watchdog is triggered
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4929B-AUTO-01/07
Figure 15-2. Functional Principle of RESQ, RESQ2
VEVZGOOD
t
"VPERI-OK"
t
"VCORE-OK"
t
RESQ 16 ms
t
chip internal trigger window
4 ms 4 ms
16 ms
WD cyc*
WD cyc*
t
Trg Wdg CMD
Trg Wdg CMD
Trg Wdg CMD
any different SPI CMD
re-configure prescaler
SPI communication
t
Re-configure prescaler while 1 st and 2nd trigger watchdog command RESQ2
t
* Watchdog cycle, see pages 48 and 49
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The RESQ2 signal results from a logical AND of the Reset signal and an OK signal from the watchdog circuitry, so RESQ2 will go high after the watchdog triggers correctly. RESQ and RESQ2 have to be set to low if VVPERI or VEVZ are below the specified threshold. VCORE is designed as an essential supply for a microcontroller core, and therefore special supervisor circuits for this regulator will affect the signals at pin RESQ and RESQ2 such that both outputs are set to low if the voltage at pin VCORE spends more than 4 regulator cycles in an overvoltage or undervoltage condition at their corresponding switching marks. In addition, a detected overcurrent signal during switch-on gives information about regulator problems, and results in a low-level signal for RESQ/RESQ2. Figure 15-3. Functional Principle of the Supervisor Circuit for VCORE Monitoring (Values are Valid for VVCORE = 1.88V and VVPERI = 3.3V)
EVZ
HIGH: 7.5V to 9V LOW: 5.5V to 6V
+ + +
VPERI
3.0V to 3.16V
3.44V to 3.6V
VCORE
1.68V to 1.73V
+
DQ CLK
DQ CLK
DQ CLK
DQ CLK
RESQ Regulator ON
2.03V to 2.08V
+ -
DQ CLK
DQ CLK
DQ CLK
DQ CLK
Regulator OFF
Signal overcurrent VCORE at regulator ON
ON
OFF
OFF VCORE Voltage ON ON
If the watchdog is triggered incorrectly, RESQ and RESQ2 are set to low as well. Voltage spikes on EVZ smaller than or equal to 10 s to 20 s do not influence the RESQ or RESQ2 pins. If the ATA6264 internal supply voltage (VINT) is below its proper value, RESQ and RESQ2 are also set to low. For all voltages at VPERI below the reset threshold, pins RESQ and RESQ2 are switched to low. Both pins deliver a valid low until VPERI goes lower than 1V. 43
4929B-AUTO-01/07
Table 15-1.
VPERI < 1V
Reset Truth Table
VCORE X X VVCORE = Not OK VEVZ X X X WATCHDOG X X X After startup (no trigger has occurred) VVCORE = OK EVZGOOD = high (VEVZ = OK) Correctly triggered (trigger occurred 1st time) Correctly triggered Incorrectly triggered X EVZGOOD = low (VEVZ = Not OK) X RESQ Undefined (low via resistor) Low Low High High High High -> low Low RESQ2 Undefined (low via resistor) Low Low Low Low -> high High High -> low Low
1V to VVPERI = OK
> VVPERI = OK
Figure 15-4. Application Example
VEVZ
VEVZ is above reset "threshold"
VCORE
VCORE is above reset "threshold" and below overvoltage RESQ
Microcontroller dual voltage supply (1.88V, 3.3V)
VPERI
VPERI is above reset "threshold" and below overvoltage
Safety system monitoring microcontroller (3.3V)
RESQ2
WD-logic
Watchdog is triggered Other peri (3.3V)
Necessary for operation: VEVZ = 5.5V to 40V, VPERI = 1V to 5.5V, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VK30, VSAT, and VCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
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Table 15-2. Electrical Characteristics - Reset Function (Pin RESQ and Pin RESQ2)
Test Conditions IRESQ, IRESQ2 = -200 A to 0 A IRESQ, IRESQ2 = 0 mA to 2 mA Pin RESQ RESQ2 RESQ RESQ2 VCORE VCORE VCORE VCORE VCORE VCORE Symbol VRESQ VRESQ2 VRESQ VRESQ2 VVCORE dVVCORE VVCORE dVVCORE VVCORE dVVCORE Min VVPERI - 0.8 0 4.5 0.17 2.25 0.1 1.68 0.07 Typ. Max. VVPERI 0.4 5.03 0.7 2.5 0.35 1.8852 0.275 Unit V V V V V V V V Type* A A A A A A A A
No. Parameters 14.1 RESQ and RESQ2 high level 14.2 RESQ and RESQ2 low level
14.3 Reset threshold at pin VCORE VVCORE is set to 5V Voltage difference 14.3a VVCORE - reset threshold at VCORE (see number 14.3) Voltage difference 14.4a VVCORE - reset threshold at VCORE (see number 14.4) Voltage difference 14.5a VVCORE - reset threshold at VCORE (see number 14.5) VVCORE is set to 5V
14.4 Reset threshold at pin VCORE VVCORE is set to 2.5V VVCORE is set to 2.5V
14.5 Reset threshold at pin VCORE VVCORE is set to 1.88V VVCORE is set to 1.88V
Overvoltage at pin VCORE to 14.6 switch off the regulator and set VVCORE is set to 5V RESQ to low Voltage difference reset 14.6a threshold at VCORE (see number 14.6) - VVCORE VVCORE is set to 5V
VCORE
VVCORE
4.97
5.5
V
A
VCORE
dVVCORE
0.17
0.7
V
A
Overvoltage at pin VCORE to 14.7 switch off the regulator and set VVCORE is set to 2.5V RESQ to low Voltage difference reset 14.7a threshold at VCORE (see number 14.7) - VVCORE VVCORE is set to 2.5V
VCORE
VVCORE
2.5
2.8
V
A
VCORE
dVVCORE
0.1
0.35
V
A
Overvoltage at pin VCORE to 14.8 switch off the regulator and set VVCORE is set to 1.88V RESQ to low Voltage difference reset 14.8a threshold at VCORE (see number 14.8) - VVCORE 14.9 Reset threshold at pin VPERI 14.10 Reset threshold at pin VPERI 14.11 14.12 14.13 14.14 Overvoltage at pin VPERI to set RESQ to low Overvoltage at pin VPERI to set RESQ to low Threshold for signal EVZGOOD = OK Threshold for signal EVZGOOD = Not OK VVCORE is set to 1.88V VVPERI is set to 5V VVPERI is set to 3.3V VVPERI is set to 5V VVPERI is set to 3.3V VEVZ rising VEVZ falling
VCORE
VVCORE
1.8748
2.11
V
A
VCORE VPERI VPERI VPERI VPERI EVZ EVZ
dVVCORE VVPERI VVPERI VVPERI VVPERI VEVZ VEVZ
0.07 4.5 2.94 5.2 3.4 7.5 5.5
0.275 4.82 3.16 5.51 3.63 9 6.2
V V V V V V V
A A A A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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4929B-AUTO-01/07
Table 15-2.
Electrical Characteristics (Continued)- Reset Function (Pin RESQ and Pin RESQ2)
Test Conditions Pin RESQ RESQ2 Symbol tRESQ tRESQ2 Min Typ. Max. Unit Type*
No. Parameters Delay time for RESQ and RESQ2 to switch to low after 14.15 reaching the reset threshold of VEVZ
10
20
s
A
RESQ is switched to low 14.16 Pull-down current at pin RESQ (VRESQ = 0.4V), 1V VVPERI < 5.5V 14.17 Pull-down current at pin RESQ2 Pull-down resistor at pin RESQ, RESQ2 Output current high side RESQ, RESQ2 RESQ, RESQ2 are switched to high, VRESQ, VRESQ2 = 0V RESQ2 is switched to low (VRESQ = 0.4V), 1V VVPERI < 5.5V
RESQ
IRESQ
1
2
mA
A
RESQ2 RESQ RESQ2 RESQ RESQ2 RESQ RESQ2 RESQ RESQ2 RESQ RESQ2
IRESQ2 RRESQ RRESQ2 IRESQ IRESQ2 IRESQ IRESQ2 tRESQ tRESQ2 tRESQ tRESQ2
1
2
mA
A
14.18
0.5
1.5
M
D
14.19
-550
-250
A
A
14.20
RESQ, RESQ2 are Output current low side RESQ, switched to high, RESQ2 VRESQ, VRESQ2 = VVPERI 30-pF external capacitive load 30-pF external capacitive load
4
10
mA
A
14.21 Rise time RESQ, RESQ2 14.22 Fall time RESQ, RESQ2
4.0 0.5
s s
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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16. Watchdog Function
To verify the proper function of the microcontroller, watchdog logic is included. As the ATA6264 is powered up, the RESQ2 signal stays low until the first valid watchdog trigger is detected. Features: * Watchdog trigger has to be done via the serial interface * In case of a watchdog-trigger mismatch, the ATA6264 is set into its default state (latches, MISO status, etc.) and RESQ is set to low. * Watchdog has to be triggered cyclically (prescaler for repetition time is set via serial interface command). Default: 16-ms repetition time Figure 16-1. Watchdog Trigger Functional Principle
VCORE 5.0V 4.8V
t
RESQ
16 ms
t
chip internal trigger window
4 ms 4 ms
16 ms
WD cyc*
WD cyc*
t
Trg Wdg CMD
Trg Wdg CMD
Trg Wdg CMD
any different SPI CMD
re-configure prescaler
Serial interface communication
t
Re-configure prescaler during 1 st and 2nd trigger watchdog command
* Watchdog cycle, see pages 48 and 49
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4929B-AUTO-01/07
Requirements for successful trigger: * Minimum one valid different serial interface command between two trigger watchdog commands is necessary. Exception: First trigger watchdog command need not be preceded by a different serial interface command. * Cyclic repetition for the trigger watchdog command within 25% tolerance is necessary. Incorrect trigger causes RESQ active. The prescaler will be set to its default value with RESQ = low Initial phase: Timing for the first trigger watchdog is fixed to 16 ms after RESQ changes from low to high (trigger window 25% means 4-ms trigger window for first trigger watchdog command). After the first watchdog trigger, the prescaler can be reconfigured within a specified time window (< 1 ms). Only one configuration command is allowed in this time window. For watchdog trigger handling, the Serial Interface Reconfigure command can be chosen as a different serial interface command. Any further configuration inside or outside this time window will cause an immediate reset via RESQ. Figure 16-2. Reconfiguration Prescaler Functional Principle
Succesful reconfiguration RESQ
inactive
No succesful reconfiguration
active
t
chip internal trigger window
1 ms 1 ms
t
Serial interface communication
Trg Wdg CMD
Trg Wdg CMD
re-configure prescaler
re-configure prescaler
t
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The trigger watchdog cycle can be set to the following retrigger times: * 4 ms * 8 ms * 16 ms (default) * 32 ms * 64 ms * 128 ms Cyclic phase: Between two trigger commands a different SPI command must be seen by the SPI decoder Figure 16-3. Watchdog Trigger Functional Principle (Successful Watchdog Trigger)
RESQ inactive
t_retrigger chip internal trigger window t_retrigger t_retrigger
t
4
4
4
4
t
Serial interface communication
Trg Wdg CMD
Trg Wdg CMD
Trg Wdg CMD
Trg Wdg CMD
Additional SPI-CMD
Additional SPI-CMD
Additional SPI-CMD
t
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4929B-AUTO-01/07
Figure 16-4. Watchdog Trigger Functional Principle (Unsuccessful Watchdog Trigger)
RESQ inactive inactive
active t_retrigger chip internal trigger window t_retrigger
active
t
4
4
4
4
t
Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD
Missing additional serial interface command additional serial interface command
Serial interface communication
t
RESQ inactive inactive
active chip internal trigger window t_retrigger t_retrigger
active
t
4
4
4
4
t
Serial interface communication
Trg Wdg CMD
Trg Wdg CMD
Trg Wdg CMD
additional serial interface command
Trg Wdg CMD
t
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Configuration of watchdog trigger: For the configuration of the watchdog prescaler, a special serial interface command is necessary.
MSByte Description Configure prescaler Note: 7 0 6 1 5 1 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1
LSByte 4 1 3 0 2 a 1 b 0 c Hex Code 60Fx
a, b, and c to be set as defined in Table 16-1
Table 16-1.
a 0 0 0 0 1 1 1 1
Watchdog Prescaler Command
Selection Bits b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 Retrigger Time (ms) Set to default (16 ms) 4 8 16 32 64 128 Set to default (16 ms)
The status of the watchdog prescaler is indicated in the status register.
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4929B-AUTO-01/07
Necessary for operation: VPERI > Reset threshold, VCORE > Reset threshold Operating conditions of all other supply pins: VK30, VEVZ and VVSAT are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 16-2.
Electrical Characteristics - Watchdog Function
Test Conditions Pin Symbol fos RESQ tRESQ Min -5% 16 Typ. 100 Max. +5% 16 Unit kHz 100 --------f os 100 --------f os 100 --------f os 100 --------f os Type* A A
No. Parameters 15.1 Oscillator frequency 15.2 Power-up extension of RESQ signal
Start of first watchdog trigger 15.3 window after rising edge at RESQ 15.4 Maximum width of first watchdog-trigger window
t
12
12
A
t
8
8
A
Maximum time for prescaler 15.5 configuration after first watchdog-trigger command 15.6 Programmed watchdog cycle 15.7 15.8 Start of programmed watchdog window Max. programmed window duration Time for RESQ = low after watchdog timeout (Missing watchdog trigger) RESQ tWD as set by prescaler (default 16 ms)
t
1
1
A
tWD 75% x tWD 50% x tWD t 16
tWD 75% x tWD 50% x tWD 16 100 --------f os
A A A
15.9
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Figure 16-5. Watchdog Trigger
VCC 5.0V 4.75V
t
RESQ 15.2 ms 15.9 ms
t
15.4 ms chip internal trigger window 15.8 ms
15.3 ms
15.7 ms 15.5 ms
15.6 ms
t
any different serial interface command
Trg Wdg CMD
Trg Wdg CMD
Trg Wdg CMD
Serial interface communication
re-configure prescaler
t
Re-configure prescaler during 1 st and 2nd trigger watchdog command
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17. LIN/ISO 9141 Interfaces
The ATA6264 includes two complete ISO 9141 interfaces. Interface #1 is controlled via the pins RxD1 and TxD1, interface #2 is controlled via the pins RxD2 and TxD2. In order to support both ISO9141 and LIN bus requirements, interface #1 can be configured during initial programming. In applications where one or both ISO9141 interfaces are not needed, the output transistors of K1 and K2 may be used as simple low-side transistors, switched on or off by the serial interface. In this mode, a diagnosis of the pins K1 and K2 via the analog multiplexer is possible. The K1 and K2 outputs include an internal current limitation and overtemperature protection circuit. Figure 17-1. Functional Principle of the LIN/ISO 9141 Interfaces
UZP C Analog input
Serial interface Analog MUX K30
Mode select K TXD
GNDB
RXD
+ 0.5 x VK30
Necessary for operation: VEVZ = 9V to 40V, VK30 = 5.5V to 40V, VVPERI > Reset threshold, VVCORE > Reset threshold, VVINT = 3.7V to 5.47V Operating conditions of all other supply pins: VVSAT is within functional range limits, Tj = -40C to +150C Other pins: As defined in Section 4. "Functional Range" on page 8.
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Table 17-1.
No.
Electrical Characteristics - LIN/ISO 9141 Interfaces
Test Conditions Pin Symbol Min Typ. Max. Unit Type*
Parameters Pull-up current to VPERI at pin TxDx Kx input receiver low Kx input receiver high Kx input receiver threshold Kx input receiver hysteresis Kx output sink current Kx output voltage drop Kx output capacitance Kx output current limitation
General (Valid for All Modes) 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 (x = 1, 2) (x = 1, 2) (x = 1, 2) (x = 1, 2) (x = 1, 2) (x = 1, 2), K output voltage 1.5V (x = 1, 2), IKx = 0 mA to 40 mA (x = 1, 2), capacitance between Kx and GNDB (x = 1, 2) (x = 1, 2), output driver deactivated (x = 1, 2), with IRxDx = 0 A to -500 A (x = 1, 2), IRxDx = 0 mA to 1mA (x = 1, 2), VRxDx = 0V (x = 1, 2), VRxDx = VVPERI (x = 1, 2), 30-pF external load (x = 1, 2), 30-pF external load TxDx Kx Kx Kx Kx Kx Kx Kx Kx Kx RxDx RxDx RxDx RxDx RxDx RxDx TxDx TxDx TxDx TxDx TxDx ITxDx VKx VKx VKx VKx IKx VKx CKx IKx IKx VRxDx VRxDx IRxDx IRxDx tRxDx tRxDx VTxDx VTxDx VTxDx VTxDx CTxDx TJKx DTJKx 155 5 100 0.5 x VVPERI 0.6 x VPERI 50 -10 VVPERI - 0.8 0 -1.1 1 0.07 x VK30 35 1.7 10 100 +10 VVPERI 0.4 -0.2 4 1 1 VVPERI + 0.3V VPERI + 0.3V 0.2 x VVPERI 550 5 185 25 -35 0 0.6 x VK30 VK30 / 2 0.2 x VK30 -50 -65 0.4 x VK30 VK30 A V V V V mA V pF mA A V V mA mA s s V V V mV pF C K A A A A A A A D A A A A A A A A A A A A D B B
16.10 Kx leakage current 16.11 RxDx voltage drop high side 16.12 RxDx voltage drop low side 16.13 RxDx high-side output current
16.14 RxDx low-side output current 16.15 RxDx output rise time 16.16 RxDx output fall time 16.17 16.18
TxDx input-voltage high-level (VPERI = 5V), threshold (x = 1, 2) TxDx input-voltage high-level (VPERI = 3.3V), threshold (x = 1, 2) (VPERI = 3.3V), (x = 1, 2) (x = 1, 2) (x = 1, 2) (x=1, 2)
16.19 TxDx input-voltage low level
16.20 TxDx input-voltage hysteresis (x = 1, 2) 16.21 TxDx input capacitance 16.22 Kx thermal shutdown 16.22a Kx thermal-shutdown hysteresis
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Table 17-1.
No.
Electrical Characteristics (Continued)- LIN/ISO 9141 Interfaces
Test Conditions Pin Kx (x = 1, 2), measured from TxDx H to L to Kx = 0.9 x VK30 RKx = 510 to K30, CKx = 470 pF to GNDB (x = 1, 2), measured from TxDx L to H to Kx = 0.1 x VK30 RKx = 510 to K30, CKx = 470 pF to GNDB (x = 1, 2), measured from 0.1 x VK30 to 0.9 x VK30 RKx = 510 to K30, CKx = 470 pF to GNDB (x = 1, 2), measured from 0.9 x VK30 to 0.1 x VK30 RKx = 510 to K30, CKx = 470 pF to GNDB (x = 1, 2), measured from Kx = 0.4 x VK30 to RxDx = H to L (x = 1, 2), from Kx = 0.6 x VK30 to xDx = L to H (x = 1, 2), tSYM_Tx = (tPDtL + tKfall) - (tPDtH + tKrise) (x = 1, 2), tSYM_Rx = tPDkL - tPDkH Measured between high level = 0.8 x VK30 and low level = 0.2 x VK30, RK1 = 1 k to K30, CK1 = 3.3 nF to GNDB Measured from TxD1 H-> L to K1 = 0.9 x VK30 RK1 = 1 k to K30, CK1 = 3.3 nF to GNDB Symbol fKx Min 62.5 Typ. Max. Unit kBd Type* A
Parameters
ISO 9141 Mode 16.23 Maximum baud rate
16.24
Propagation delay TxDx = low to Kx = low
Kx
tPDtL
1
s
A
16.25
Propagation delay TxDx = high to Kx = high
Kx
tPDtH
1
s
A
16.26 Kx rise time
Kx
tKrise
3
s
A
16.27 Kx fall time
Kx
tKfall
3
s
A
16.28
Propagation delay Kx = low to RxDx = low Propagation delay Kx = high to RxDx = high Symmetry of transmitter delay Symmetry of receiver propagation delay
Kx
tPDkL
4
s
A
16.29
Kx
tPDkH
4
s
A
16.30
Kx Kx
tSYM_Tx tSYM_Rx
-1
1
s
A
16.31
-1
1
s
A
LIN Bus Mode (Necessary for Operation: VK30 = 8V to 18V) Slew rate for rising and falling edge
16.32
K1
dVK1/dt
1
3
V/s
A
16.33 Maximum baud rate Propagation delay TxD1 low to K1 = low
K1 K1
tKx tPDtL
20
kBd
A
16.34
2.5
s
A
Measured from TxD1 Propagation delay TxD1 high L to H to K1 = 0.1 x VK30 16.35 to K1 = high RK1 = 1 k to K30, CK1 = 3.3 nF to GNDB 16.36 Propagation delay K1 low to RxD1 = low Measured from K1 = 0.4 x VK30 to RxD1 = H to L
K1
tPDtH
2.5
s
A
K1
tPDkL
4
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Table 17-1.
No. 16.37
Electrical Characteristics (Continued)- LIN/ISO 9141 Interfaces
Test Conditions Pin K1 K1 K1 Symbol tPDkH tSYM_T1 tSYM_R1 -1 -1 Min Typ. Max. 4 Unit s Type* A
Parameters
Measured from Propagation delay K1 high to K1 = 0.6 x VK30 to RxD1 = high RxD1 = L to H Symmetry of transmitter delay Symmetry of receiver propagation delay tSYM_T1 = tPDtL - tPDtH tSYM_R1 = tPDkL - tPDkH
16.38 16.39
1 1
s s
A A
LS Driver Mode 16.40 Kx output voltage drop IKx = 40 mA IKx = 20 mA (x = 1, 2), measured from rising edge of SSQ to VKx = 16.40V, RKx = 250 to K30, CKx = 3.3 nF to GNDB (x = 1, 2), measured from rising edge of SSQ to VKx = 0.9 x VK30, RKx = 250 to K30, CKx = 3.3 nF to GNDB (x = 1, 2), output driver deactivated, AMUX measurement activated and deactivated K30 = 5.5V to 15V K30 > 15V to 25V K30 > 25V to 40V (x = 1, 2), output driver deactivated, AMUX measurement deactivated K30 = 5.5V to 40V Kx = -25V Kx VKx 1.7 1.2 V A
16.41 Kx switch-on delay
Kx
tKx
50
s
A
16.42 Kx switch-off delay
Kx
tKx
10
s
A
16.43 Kx leakage current
Kx
IKx -10 -10 -10 +100 +160 +260 A A A A A A
16.44 Kx leakage current
Kx
IKx
-150
+10
A
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 17-2. Timing LIN/ISO 9141 Interface
2 Baudrate VTXD 2 ton + toff
Baudrate =
VK tPDtL
90% 60% 40% 10%
tPDtH
VRXD
tPDkL
tPDkH
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18. Voltage/Current Sources (IASGx Sources)
For a variable resistance measurement and especially for buckle-switch detection, five constant voltage sources, switchable between two different voltages (V1 and V2) are implemented. The current delivered by these voltage sources is mirrored by a factor of 1 / 10 or 1 / 15 to the pin ISENS and causes a voltage drop at the external resistor connected to this pin. This voltage drop can be measured at pin UZP by choosing the corresponding AMUX command. The external resistor at pin IASGx can be calculated using the following formulas:
V V1 - V V2 R ISENS R IASGx = ----------------- x ---------------------------------------------- or V ISENS1 - V ISENS2 10 V V1 - V V2 R ISENS R IASGx = ----------------- x ---------------------------------------------15 V ISENS1 - V ISENS2
The current through pin IASGx is internally limited to a value between IIASGx = -150 mA and -50 mA. If the voltage at pin ISENS becomes higher than VVPERI, the voltage at pin IASG and, consequently, the current at pin IASGx is reduced until VISENS = VVPERI. This function can be used to reduce the current limitation of pin IASGx to values lower than the internal limit by choosing an adequate external resistor at pin ISENS. In this case, the maximum current through pin IASGx can be calculated as:
V VPERI I IASGxlim = 10 x ----------------- or R ISENS V VPERI I IASGxlim = 15 x ----------------R ISENS
For high accuracy, the IASGx current needs to be between 0.5 mA and 40 mA, and the maximum ISENS voltage must be < VPERI - 40%. Under a clamping condition, the voltage at pin ISENS is clamped to VPERI + 5%. Calculation of the resistor at pin ISENS:
CR1 RSENS = 0.96 x V PERI x ------------------I ASGmax
In applications with one or more unused IASG channels, the IASG pins can be used as measurement inputs. The five IASG pins are connected to the analog multiplexer block via different dividers. Voltages applied to these IASG pins can be measured at the UZP pin, selected via SPI commands.
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Figure 18-1. Functional Principle of the IASG Interface
Serial interface Serial interface 10 1
Current mirror
15
1
Short circuit protection VV1 VV2
Serial interface Current limit if VISENS >VPERI UZP
+ -
Analog multiplexer
IASGx I = f(R) C > 10 pF Resistive sensor RIASGx
ISENS I/10 or I/15 RISENS
Necessary for operation: VVCORE and VVPERI > Reset threshold, VEVZ = 9V to 40V for operation with IASGx switched to 5V VVCORE and VVPERI > Reset threshold, VEVZ = 15V to 40V for operation with IASGx switched to 10V VINT = 3.7V to 5.47V, VCP > VEVZ + 7V Operating conditions of all other supply pins: VK30 and VVSAT are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8, CIASGx 10 nF and 825 RISENS 5 k
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Table 18-1.
Electrical Characteristics - Voltage/Current Sources (IASGx Sources)
Test Conditions (x = 1 to 5), -40 mA < IIASGx < -0.5 mA VISENS = 0.96 x VVPERI (x = 1 to 5), -40 mA < IIASGx < -0.5 mA VISENS = 0.96 x VVPERI IASGx switched to 5V VEVZ > 11V (x = 1 to 5), -25 mA < IIASGx < -0.5 mA VISENS = 0.96 x VVPERI IASGx switched to 5V VEVZ > 9V to 11V (x = 1 to 5) when IASG = 5V when IASG = 10V (x = 1 to 5), with VIASGx = 10V / 0.5 mA < RLOAD < VIASGx = 5V / 40 mA Pin IASGx Symbol V1IASGx Min -6% Typ. 10 Max. +6% Unit V Type* A
No. Parameters 17.1 Output voltage (V1)
17.2 Output voltage (V2)
IASGx
V2IASGx
-6%
5
+6%
V
A
17.2a Output voltage (V2)
IASGx
V2IASGx
-6%
5
+6%
V
A
Output voltage overshoot at 17.3 IASGx due to regulator characteristic 17.4 Maximum duration of voltage overshoot at IASGx
IASGx
VIASGx
5.9 11.3 30
V V s
A A A
IASGx IASGx IASGx
tIASGx IIASGx IIASGx -40 -150
17.5 17.6
Linear range for current mirror (x = 1 to 5), at IASGx 0V = VISENS = 0.96 x VPERI Internal current limitation at IASGx (x = 1 to 5) (x = 1 to 5), CR1x = IIASGx / IISENS 0V = VISENS = 0.96 x VVPERI -40 mA < IIASGx< -0.5mA (x = 1 to 5), CR2x = IIASGx / IISENS 0V = VISENS = 0.96 x VVPERI -40 mA < IIASGx < -0.5 mA (x = 1 to 5), RIASGx = 250, no capacitive load at IASGx (x = 1 to 5) Measured from rising edge of SSQ to VIASGx = 0.1 x VIASGx RIASGx = 250, no capacitive load at IASGx
-0.5 -50
mA mA
A A
17.7 Current ratio #1
IASGx
CR1x
-3%
9.9
+3%
A
17.8 Current ratio #2
IASGx
CR2x
-3%
14.9
+3%
A
17.9 Settling time
ISENSE
tISENSE
0
50
s
A
17.10 Switch-on delay
IASGx
tIASGx
0
50
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Table 18-1. Electrical Characteristics (Continued)- Voltage/Current Sources (IASGx Sources)
Test Conditions IIASGx > CRY x VVPERI / RISEN 17.11 Output voltage clamping (VISENS VVPERI)
S
No. Parameters
Pin
Symbol
Min 0.96 x VVPERI -1.6 -1.6
Typ.
Max. 1.05 x VVPERI +1.6 +1.6
Unit
Type*
(x = 1 to 5), (Y = 1, 2) (VISENS VVPERI regulator active) VISENS = 0V to 0.96 x VVPERI (x = 1 to 5) IASGx channel deactivated, 0V < VIASGx < VEVZ
ISENSE
VISENSE
V
A
17.12 ISENS leakage current 17.13 IASGx leakage current
ISENSE IASGx
IISENSE IIASGx
A A
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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19. AMUX (Analog Multiplexer for Voltage Measurements)
Various voltages and the chip temperature inside of the ATA6264 can be measured at the analog measurement output UZP. Different voltage dividers ensure that the values of the measured voltages at UZP are in the range of 0V to VPERI. To select a specific measurement, a serial interface command has to be sent to the ATA6264. For the list of measurable voltages and temperatures, refer to Section 22. "Serial Interface Commands" on page 68. The overall accuracy of the measurement part inside the ATA6264 can be calculated using the following formula: V meas V UZP = ------------------------------------------------------- V UZPoffset ratio ratio tolerance
Figure 19-1. AMUX Tolerances
max.
VUZP
VUZP_max typ.
min. VUZP_min
VUZP_offset Vmeas Vin
In order to describe the behavior of the whole measurement properly, the tolerance of the voltage-divider ratio (ratio tolerance) and the offset tolerance of the UZP buffer (V UZPoffset) are defined in separate points. The UZP buffer is defined in the following section. Necessary for operation: VEVZ = 8V to 40V or VCP = 10V to 50V, VVINT = 3.7V to 5.47V Operating conditions of all other supply pins: VK30, VVSAT, VVPERI and VVCORE are within functional range limits, Tj = -40C to +150C Other pins: As defined in Section 4. "Functional Range" on page 8.
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Table 19-1.
No. 18.1
Electrical Characteristics - AMUX (Analog Multiplexer for Voltage Measurements)
Test Conditions Has to be calculated from the values of the differential measurement For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = 5V For VVPERI = 3.3V For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = VVCORE = 5V For VVPERI > VVCORE VVPERI - 0.2V VISENS 0.2V For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = 5V For VVPERI = 3.3V For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) Pin UZP Symbol VUZPoffset Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Min -5 6.05 4% 6.05 2.3% 9.12 6% 9.12 2.3% 6.04 6% 6.04 2.3% 9.11 6% 9.11 2.3% 9.9 2.3% 14.78 2.6% 6.05 6% 6.05 2.3% 9.12 6% 9.12 2.3% 2 2.3% 0.995 1% 0.992 1% 6.06 3.5% 6.06 2.3% 9.16 3.5% 9.16 2.3% 6.06 3.5% 6.06 2.3% 9.16 3.5% 9.16 2.3% 10 3% 14.75 3% 6.04 6% 6.04 2.3% 9.11 6% 9.11 2.3% 6.04 6% 6.04 2.3% 9.11 6% 9.11 2.3% 6.04 6% 6.04 2.3% 9.11 6% 9.11 2.3% 0.995 1% Typ. Max. +15 Unit mV Type* A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Parameters Output offset error
18.2
Ratio VK15 / VUZP
UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP UZP
18.2a Ratio VK15 / VUZP 18.3 Ratio VK30 / VUZP
18.3a Ratio VK30 / VUZP 18.4 Ratio VEVZ / VUZP
18.4a Ratio VEVZ / VUZP 18.5 Ratio VSAT / VUZP
18.5a Ratio VSAT / VUZP 18.6 18.7 18.8 Ratio VVCORE / VUZP Ratio VISENS / VUZP Ratio VK1 / VUZP
18.6a Ratio VVCORE / VUZP
18.8a Ratio VK1 / VUZP 18.9 Ratio VK2 / VUZP
18.9a Ratio VK2 / VUZP 18.10 Ratio VIASG1 / VUZP 18.10a Ratio VIASG1 / VUZP 18.11 Ratio VIASG2 / VUZP 18.11a Ratio VIASG2 / VUZP 18.12 Ratio VIASG3 / VUZP 18.12a Ratio VIASG3 / VUZP 18.13 Ratio VIASG4 / VUZP 18.13a Ratio VIASG4 / VUZP 18.14 Ratio VIASG5 / VUZP
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Table 19-1.
No.
Electrical Characteristics (Continued)- AMUX (Analog Multiplexer for Voltage Measurements)
Test Conditions For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) Pin UZP UZP Symbol Ratio Ratio Min Typ. Max. Unit Type* A A A A A A A 6.02 6% 6.02 2.3% 9.07 6% 9.07 2.3% 3.99 2.6% (0.9 x VVPERI) 2% (0.1 x VVPERI) 2% 6 40 V
Parameters
18.15 Ratio VUSP / VUZP 18.15a Ratio VUSP / VUZP
Special Measurement (For Detection of Band-gap Defect) 18.16 Ratio VVINT / VUZP 18.17 18.18 Voltage 0.9 x VVPERI switched to VUZP Voltage 0.1 x VVPERI switched to VUZP UZP UZP UZP Ratio Ratio Ratio
Input voltage range for 18.19 proper function of 10 or 14.6 divider Input voltage range for 18.20 proper function of 6 or 9.1 divider Input voltage range for 18.21 proper function of 4 and 2 divider 18.22 Input voltage range for proper function of 1 buffer
VInput
A
VInput
1.5
25
V
A
VInput VInput
4
6 VVPERI - 0.2 1 0%
V
A
0.2 -2%
V
A A
18.23 Ratio VREF / VUZP
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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20. UZP Buffer
The pin UZP is an analog output pin of the ATA6264. The UZP buffer is realized as a tristate output with the ability to drive to VPERI as well as to GNDA. The selected measurement result is given to the pin UZP as long as no new measurement is selected or the tristate command has been sent. Driver capability is typically 4 mA. Figure 20-1. Functional Principle of the UZP Buffer
VVPERI Tristate / normal operating 2 to 8 mA
Voltage selected voltage from AMUX
Driver circuitry UZP 470 to 2000
Driver circuitry
1 to 47 nF
2 to 8 mA GNDA
Necessary for operation: VPERI > Reset threshold, VCP = 10V to 50V, VVINT = 3.7V to 5.47V Operating conditions of all other supply pins: VK30, VEVZ, VVSAT and VVCORE are within functional range limits, TJ = -40C to +150C Other pins: As defined in Section 4. "Functional Range" on page 8.
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Table 20-1.
Electrical Characteristics - UZP Buffer
Test Conditions VUZP = 0V, UZP connected to GND Pin UZP Symbol IUZP Min -8 Typ. Max. -2 Unit mA Type* A
No. Parameters Output current high side, 19.1 driving current with measurement activated
Output current low side, V = VVPERI 19.2 sink current with measurement UZP UZP connected to GND activated 19.3 Output settling time Measured from rising edge of SSQ to 90% of VUZP, no load at pin UZP Load 2 k/22 nF low-pass filter connected to pin UZP, measured from rising edge of SSQ to 90% of VLow pass filter out
UZP
IUZP
2
8
mA
A
UZP
tUZP
10
s
A
19.4 Output settling time
UZP
tUZP
250
s
A
19.5 Output resistance 19.6 Linear measurement range VIASG5 switched via AMUX to UZP, VIASG5 = 6V VUZP = 0V to VVPERI, UZP buffer in tristate mode UZP buffer in tristate mode
UZP UZP
RUZP VUZP VUZP IUZP CUZP tUZP 0.2 VVPERI - 50 mV -5 0
100 VVPERI - 0.2 VVPERI + 50 mV +5 10 3
V
A A
19.7 Maximum output voltage
UZP
V
A
19.8 Output leakage current 19.9 Output capacitance
UZP UZP UZP
A pF s
A D A
Measured from rising edge 19.10 Time to switch to tristate mode of SSQ to Ileak within tolerance
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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21. Chip Temperature Measurement
A serial interface command allows measuring a chip-temperature-dependent voltage which is generated by two diodes connected in series. Three 2-diode sensors are connected in parallel and located in the following blocks: VPERI, VCORE, and VSAT. The diodes are supplied by a temperature-constant current source, the voltage drop of the diodes is switched via AMUX to pin UZP. If the overtemperature level is exceeded, bit a7 in the status register is set to "1". Necessary for operation: VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VK30, VEVZ, VVSAT, VVPERI and VVCORE are within functional range limits, Tj = -40C to 150C Other pins: As defined in Section 4. "Functional Range" on page 8.
Table 21-1.
Electrical Characteristics - Chip Temperature Measurement
Test Conditions Chip temperature switched via AMUX to UZP Chip temperature switched via AMUX to UZP, TJ = 25C If overtemperature is detected, voltage drops by 35 mV Pin UZP UZP Symbol VUZP VUZP VUZP VUZP Min -4 1.29 Typ. -3.6 Max. -3.2 1.54 Unit mV/K V Type* D A
No. Parameters 20.1 20.2 Temperature coefficient of chip-temperature sensor Output voltage temperature sensor Threshold overtemperature detection Hysteresis for overtemperature detection
20.3
UZP
155
185
C
B
20.3a
UZP
5
25
K
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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22. Serial Interface Commands
22.1 Overview
All functions of the ATA6264 are triggered by 16-bit serial interface commands. Some of these commands are latched because their actions have to continue for a longer time. Other commands have to be executed as long as no other command is received via the serial interface. The pin SSQ (low active) is used to select the ATA6264. If pin SSQ is inactive (high), the output pin MISO is disabled (tristate) and the signals at the pins SCLK and MOSI are ignored and do not affect the data in the serial interface register. With the falling edge at pin SSQ, the ATA6264 response on the previous command is latched in the ATA6264 status register and, after a short delay time, the signal at pin MISO is valid. With the rising edge at pin SCLK, the data at pin MOSI is shifted into the serial interface input register and the next bit of the status register is shifted to pin MISO. A command received at pin MOSI is valid and will be executed if the number of rising edges at pin SCLK was exactly 16 during data transmission; otherwise, the received signal will be ignored. The slave select pin, SSQ, allows the individual selection of different slave SPI devices. Slave devices that are not selected do not interfere with SPI bus activities. To ensure deactivation of the device in case of an open SSQ pin, an internal current source is implemented to drive the SSQ pin to high level (VPERI). All commands, independent of their function, consist of 16 bits. The serial interface includes a 16-bit input shift register, 16-bit latches, and a decoder logic block for the generation of the SPI command signals. To suppress data transfer errors in the case of spikes or glitches on the clock signal, a 16-clock-cycle counter is provided. Only after 16 clock cycles does the rising edge of SSQ cause an internal signal latch enable, which transfers the data from the shift register to the 16-bit latch. The data word is decoded to address the correct functional block.
Table 22-1.
Electrical Characteristics - Serial Interface Commands
Test Conditions Pin SCLK SSQ SSQ, SCLK, MOSI
(2)
No. Parameters 21.1 SSQ to SCLK rising-edge isolation
Symbol tiso tlag tf tf tr tr tsu thold
Min 100 100
Typ.
Max.
Unit ns ns
Type* A(3) A(3) A(3) A A(3) A A(3) A(3)
21.2 SSQ lag time 21.3 Fall time 21.3a Fall time 21.4 Rise time 21.4a Rise time 21.5 Data set-up time 21.6 Data hold time Note:
(2)
20 20 20 20 20 20
ns ns ns ns ns ns
MISO SSQ, SCLK, MOSI MISO MOSI MOSI
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Voltage levels for serial interface timing measurements: High level = 0.7 x VVPERI, low level = 0.2 x VVPERI 2. Timing specified with a 100-pF external load at pin MISO 3. System requirement
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Table 22-1. Electrical Characteristics (Continued)- Serial Interface Commands
Test Conditions
(2)
No. Parameters 21.7 21.8 21.9 21.10 Time from SSQ falling edge to MISO MSB valid Time from SCLK rising edge to MISO valid Time from SSQ rising edge to MISO tristate condition No-data time between serial interface commands
Pin MISO MISO MISO
Symbol tMISOMSB_V tMISOV tMISOhiZ tnodata
Min 0 0 0 1.5 0 -95 -95 40
Typ.
Max. 400 40 40
Unit ns ns ns s
Type* A A A A(3) A(3) A A A(3) A A
(2)
(2)
21.11 Clock frequency 21.12 Pull-up current VPERI 21.13 Pull-up current VPERI 21.14 SCLK high/low time 21.15 Input voltage high level 21.16 Input voltage low level 21.17 Input voltage hysteresis 21.18 Output voltage high level 21.19 Output voltage low level 21.20 21.21 IMISO = -1 mA to 0 mA IMISO = 0 mA to 1 mA
CLK SSQ SCLK SCLK SSQ, SCLK, MOSI SSQ, SCLK, MOSI SCLK MISO MISO MISO MISO SSQ, SCLK, MOSI Switched-off condition Switched-off condition MISO MISO
fSCLK Rpu_SSQ Rpu_SCLK tCL VH VL VHYS VH VL IMISO IMISO CIN CMISO IMISO
8 -45 -45 0.5 x VVPERI
MHz A A ns
0.25 x VVPERI 50 VVPERI - 0.8 0 -47 6 250 VVPERI 0.4 -10 45 10 10 -10 +10 mV V V mA mA pF pF A
A A A A A D D A
Output current high level driven VVPERI = 5V to short circuit Output current low level sinking VVPERI = 5V from VPERI level
21.22 Input capacitance 21.23 Output capacitance 21.24 Leakage current Number of clock cycles to be detected between falling and 21.25 rising edge of SSQ, to set error signal in status register to "0" Note:
16
16
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Voltage levels for serial interface timing measurements: High level = 0.7 x VVPERI, low level = 0.2 x VVPERI 2. Timing specified with a 100-pF external load at pin MISO 3. System requirement
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Figure 22-1. Timing Serial Interface
10. (> 1.5 s)
SSQ
4. (< 20 ns) 3. (< 20 ns) 14. (> 40 ns) 2. (> 100 ns) 1. (> 100 ns)
SCLK
#1
5. (> 20 ns) 6. (> 20 ns)
#16
MOSI
not defined 7. (< 400 ns)
not defined
MSB 8. (< 40 ns)
LSB 9. (< 40 ns)
not defined
MISO
MSB
LSB
22.2
Set Commands
After a reset due to the watchdog or undervoltage, all internal control registers and decoded signals are set to their default values.
Table 22-2.
Set of Serial Interface Commands
MSByte LSByte Option and Data 7654321076543210
Command NOP Key latch Watchdog Switch commands Initial programming Diagnosis IASG Test mode 1 Test mode 2 Test mode 3 Test-mode enable
Latch No Yes No Yes N/A No No No No No No
Hex 0000 3xxx 6xxx 9xxx Axxx Cxxx Fxxx 55AA AA55 5500 5A5A
Description
Command
0000000000000000 See Table 22-3 on 0011xxxxxxxxxxxx page 71 See Table 22-4 on 0110xxxxxxxxxxxx page 71 See Table 22-5 on 1001xxxxxxxxxxxx page 71 See Table 22-6 on 1010xxxxxxxxxxxx page 72 See Table 22-7 on 1100xxxxxxxxxxxx page 72 See Table 22-8 on 1111xxxxxxxxxxxx page 73 0101010110101010 1010101001010101 0101010100000000 0101101001011010
Serial interface commands other than those listed in Table 22-2 on page 70 lead to an interruption of measurements via AMUX, cause pin UZP to be switched to tristate, and IASG sources to be deactivated. The status of the latches does not change.
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Table 22-3.
Description Key latch set Key latch reset (default)
Key Latch Commands
MSByte 7 0 0 6 0 0 5 1 1 4 1 1 3 1 0 2 1 0 1 1 0 0 1 0 7 1 0 6 1 0 5 1 0 LSByte 4 1 0 3 1 0 2 1 0 1 1 0 0 1 0 Hex Code 3FFF 3000
Table 22-4.
Description
Watchdog Commands
MSByte 7 0 0 6 1 1 5 1 1 4 0 0 3 1 0 2 0 0 1 1 0 0 0 0 7 0 1 6 1 1 5 0 1 LSByte 4 1 1 3 0 0 2 1 a 1 0 b 0 1 c Hex Code 6A55 60Fx
Trigger watchdog Configure prescaler
Table 22-5.
Description
Switch Commands
MSByte 7 1 1 1 1 1 1 6 0 0 0 0 0 0 5 0 0 0 0 0 0 4 1 1 1 1 1 1 3 1 0 0 0 0 0 2 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 7 0 0 1 1 0 1 6 1 0 1 0 0 1 5 0 0 1 0 0 1 LSByte 4 1 0 1 1 0 1 3 1 1 0 0 1 0 2 0 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 0 1 0 Hex Code 9A5A 930F 93F0 9396 960F 96F0
Enable EVZ switching EVZ switched to 33V EVZ switched to 23V (default) EVZ switched to external divider CP-OUT switched to high-ohmic state (default) CP-OUT switched to low-impedance state K1 interface works as ISO9141 or LIN interface (depending on ISO/LIN bit of initial programming) (default) K1 interface works in LS driver mode K1 switched to high-ohmic state (default) K1 switched to low-impedance state K2 interface works as ISO9141 interface (default) K2 interface works in LS driver mode K2 switched to high-ohmic state (default) K2 switched to low-impedance state
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
99F0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 1 1 1 1 1 1
1 1 1 1 1 1 1
0 1 1 0 0 1 1
0 0 0 0 0 0 0
1 0 0 1 1 0 0
1 1 1 0 0 0 0
1 1 1 0 0 0 0
1 1 1 0 0 0 0
1 1 1 0 0 0 0
1 0 1 0 1 0 1
1 0 1 0 1 0 1
1 0 1 0 1 0 1
1 0 1 0 1 0 1
99FF 9CF0 9CFF 9900 990F 9C00 9C0F
Because the K1 and K2 interfaces are by default switched to ISO (LIN) mode, the commands 9CF0, 9CFF, 9C00, and 9C0F default to invalid commands.
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Table 22-6.
Description
Initial Programming (IP Command)
MSByte 7 1 6 0 5 1 4 0 3 1 2 0 1 0 0 1 7 x 6 x 5 x LSByte 4 x 3 x 2 x 1 x 0 x Hex Code A9xx
Write data to IP register
The initial programming command is only available in Test mode. For more information about the programming flow and the register contents, see Section 5.2 "Initial Programming of the ATA6264" on page 11.
Table 22-7.
Description
Diagnosis Commands
MSByte 7 1 6 1 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 LSByte 4 0 3 0 2 0 1 0 0 0 Hex Code C000
Set UZP to tristate mode and switch off all measurements Switch VEVZ via AMUX to UZP Switch VVSAT via AMUX to UZP Switch 90% x VVPERI via AMUX to UZP Switch 10% x VVPERI via AMUX to UZP Switch VVCORE via AMUX to UZP Switch VK15 via AMUX to UZP Switch VK30 via AMUX to UZP Switch VIREF via AMUX to UZP Switch VIASG1 via AMUX to UZP Switch VIASG2 via AMUX to UZP Switch VIASG3 via AMUX to UZP Switch VIASG4 via AMUX to UZP Switch VIASG5 via AMUX to UZP Switch VUSP via AMUX to UZP Switch VK1 via AMUX to UZP Switch VK2 via AMUX to UZP Note:
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1
1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0
0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0
1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1
CA31 CA32 CA34 CA38 CA61 CA62 CA64 CA68 CA92 CA94 CA98 CAC1 CAC2 CAC4 CAC8 CAE1
1. UZP voltage will be influenced by the USP voltage
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Table 22-7.
Description Switch VVINT via AMUX to UZP Switch voltage at chip-temperature sensor via AMUX to UZP Note:
Diagnosis Commands (Continued)
MSByte 7 1 6 1 5 0 4 0 3 1 2 0 1 1 0 0 7 1 6 1 5 1 LSByte 4 0 3 0 2 0 1 1 0 0 Hex Code CAE2 CAE4(1)
1
1
0
0
1
0
1
0
1
1
1
0
0
1
0
0
1. UZP voltage will be influenced by the USP voltage
Because the diagnosis commands are non-latching commands, any new serial interface commands, except watchdog triggering (6A55) and the Kx switching commands (9Cxx), interrupt the diagnosis.
Table 22-8.
Description
IASG Commands
MSByte 7 1 1 1 1 6 1 1 1 1 5 1 1 1 1 4 1 1 1 1 3 0 0 0 0 2 a a a a 1 b b b b 0 c c c c 7 0 0 1 1 6 0 0 1 1 5 1 1 0 0 LSByte 4 1 1 0 0 3 0 1 0 1 2 0 1 0 1 1 1 0 1 0 0 Hex Code 1 0 1 0 Fx33 Fx3C FxC3 FxCC
IASGx switched to 10V (mirror factor 10:1) IASGx switched to 10V (mirror factor 15:1) IASGx switched to 5V (mirror factor 10:1) IASGx switched to 5V (mirror factor15:1) Note:
a, b, and c represent the IASG number in binary format; only 001 = IASG1, 010 = IASG2, 011 = IASG3, 100 = IASG4, and 101 = IASG5 are valid commands
Table 22-9.
Description
Example
MSByte 7 1 1 6 1 1 5 1 1 4 1 1 3 0 0 2 0 1 1 0 0 0 1 1 7 0 1 6 0 1 5 1 0 LSByte 4 1 0 3 0 1 2 0 1 1 1 0 0 1 0 Hex Code F133 F5CC
IASG1 switched to 10V (mirror factor 10:1) IASG5 switched to 5V (mirror factor 15:1)
Because the IASG commands are non-latching commands, any new serial interface command, except watchdog triggering (6A55) and the Kx switching commands (9Cxx), interrupts the IASG function.
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22.3
Serial Interface Status Register
For all serial interface commands except the test-mode commands (55AAh, AA55h, 5500h), the ATA6264 status is available at the MISO line. For the status register a 16-bit structure is used, one bit for each information.
Table 22-10. Status Register
Byte A MSBit a7 a6 a5 a4 a3 a2 a1 LSBit MSBit a0 b7 b6 b5 b4 b3 b2 b1 Byte B LSBit b0
Table 22-11. Information Provided by the Itemized Bits of the Status Register
Bit a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 Set To High Low High Low High Low High Low High Low High Low High Low High Low High Low High Low High Low High Low High Low Information Chip temperature reports overtemperature Chip temperature reports normal temperature Overtemperature at K1 output Normal temperature at K1 output Overtemperature at K2 output Normal temperature at K2 output Latch for GKEY function is set Latch for GKEY function is not set EVZ switched to 33V, EVZ switched to external divider EVZ switched to 23V CP-OUT switch is low impedance CP-OUT switch is high ohmic CP-OUT voltage too low CP-OUT voltage is in correct voltage range CP voltage too low CP voltage is in correct voltage range Voltage at pin USP above detection threshold Voltage at pin USP below detection threshold GNDA or GNDB disconnected GNDA and GNDB connected Previously sent serial interface command was invalid (default after power-on reset) Previously sent serial interface command was valid Error during last serial interface transmission (default after power-on reset) No error during last serial interface transmission IC is in Test mode IC is in Normal mode Reflects bit b2 of the watchdog prescaler Reflects bit b1 of the watchdog prescaler Reflects bit b0 of the watchdog prescaler
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The overtemperature bits a5, a6 and a7 are latched when overtemperature is detected. These bits will be reset with the next SPI command, unless overtemperature still exists. In the case of a reset, bits b4 and b5 are not set to their default state. These bits show the status before reset so that the microcontroller can detect whether or not the ATA6264 is in power-up state.
Table 22-12. Test Command Issued via the MISO line as a Result of the Test Mode Commands
Description Test mode 1 Test mode 2 Test mode 3 Note: Command 55AA AA55 5500 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 MISO Answer 1 0 0 0 1 1 0 1 a 1 0 b 0 1 c 1 0 d 0 1 e 1 0 f 0 1 g 1 0 h Hex Code AA55 55AA 01xx
a, b, c, d, e, f, g, h represent the contents of the Initial Programming Register
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23. Test Mode
For better testability of the ATA6264, a test mode is implemented. This mode is activated if the pins RESQ and TxD1 are connected to GND, the pins RESQ2 and TxD2 are connected to VPERI, and the serial interface command 5A5Ah is sent to the ATA6264. Test mode is latched as long as the ATA6264 is powered (VK30 > 4.2V to 5V and VK15 > 3V to 4V). In Test mode the watchdog is disabled, which means that RESQ and RESQ2 depend on the voltage levels of the pins VCORE, VPERI and EVZ. In order to provide the programming voltage at VSAT for the initial programming, VVSAT is set to 11.7V (0.5V) in Test mode if the lock bit is not set. After a reset, Test mode is disabled (default). The following serial interface commands are used for the ATA6264 supplier test: E6B5(h) and E6BA(h). Figure 23-1. How to Enable Test Mode
RESQ TxD1
RESQ2 TxD2 Enable testmode SSQ MISO SPI decoder MOSI SCLK
VPERI
5A5A (h)
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24. Application Circuits
Figure 24-1. Overview of a Typical Airbag System
K30 K15 K1 K2 IASG1 to 5
K30 K15
USP
IREF
K1
K2 IASG1 to 5
RESQ2
D, L, C net
GEVZ OCEVZ GNDB EVZ FBEVZ COMEVZ SVSAT COMSATO COMSATI VSAT VPERI VPERIFB SVCORE VCORE COMCOI COMCOO
UZP RxD2 TxD2 RxD1 TxD1 RESQ GNDD
Microcontroller Serial interface
Sensor
Safetysystem monitoring
ISENS
GNDA CP CP-OUT
Enable Firing ASIC Firing loops Enable
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Figure 24-2. Typical Application Circuit
78
RESQ RESQ2 RESQ2 SSQ Cp SSQ RESQ SCLK SCLK VINT MISO MOSI MOSI RxD1 TxD1 FBEVZ EVZ (33V) EVZ GEVZ OCEVZ COMSATO COMSATI COMCOI COMCOO RxD2 TxD2 UZP K1 K2 IASG1 IASG2 IASG3 IASG4 IASG5 ISENS CP-OUT CP-OUT IREF VCORE SVCORE VCORE (5V) GNDB GNDA GNDD SVPERI VPERI VSAT SVSAT VSAT (9V) VPERI (5V) COMEVZ RxD1 TxD1 RxD2 UZP TxD2 USP MISO K30 K15 KL15
ATA6264 [Preliminary]
ATA6264
KL30
KL30
K1
K2
4929B-AUTO-01/07
ATA6264 [Preliminary]
25. Ordering Information
Extended Type Number ATA6264-ALTW ATA6264-ALQW Package P-TQFP44 P-TQFP44 Remarks Tray Taped and reeled
26. Package Information
Package: P-TQFP 44 (acc. JEDEC OUTLINE No. MO-112) Dimensions in mm
120.2 100.05 8
0.2
44
34 0.60.15 0.10.05 1.40.05
technical drawings according to DIN specifications
1
33 0.8
11
23
12 0.37-0.07
+0.08
22
Drawing-No.: 6.543-5131.01-4 Issue: 1; 11.05.06
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27. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4929B-AUTO-01/07 History * Put datasheet in a new template * Section 23 "Test Mode" on page 76 changed
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28. Table of Contents
Features ..................................................................................................... 1 1 Description ............................................................................................... 1
1.1 Block Description .................................................................................................3 1.1.1 Integrated Boost Converter EVZ .....................................................................3 1.1.2 Integrated Buck Converter VSAT ....................................................................3 1.1.3 Integrated Buck Converter VCORE ................................................................3 1.1.4 Linear Regulator VPERI ..................................................................................3 1.1.5 Blocks Included ...............................................................................................3
2 3 4
Pin Configuration ..................................................................................... 4 Absolute Maximum Ratings .................................................................... 6 Functional Range ..................................................................................... 8
4.1 Protection Against Substrate Currents .................................................................9
5
Supply Currents ..................................................................................... 10
5.1 5.2 Discharger Circuit ...............................................................................................11 Initial Programming of the ATA6264 ..................................................................11
5.3 Start-up and Power-down Procedure .................................................................14 5.3.1 Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V ................15 5.3.2 The Power-down Procedure Takes Place in Different Phases .....................15 5.3.3 Start-up Procedure if VVCORE Programmed to Be 1.88V ...........................16 5.3.4 The Power-down Procedure for VVCORE is Programmed to be 1.88V .......17
6 7 8 9
Power Supply Sequencing .................................................................... 18 Charge Pump .......................................................................................... 20 GKEY Function ....................................................................................... 22 EVZ Step-up Regulator .......................................................................... 24
10 VSAT Power Supply ............................................................................... 30 11 VPERI Power Supply ............................................................................. 33 12 VCORE Power Supply ........................................................................... 35 13 USP Comparator for General Purpose ................................................. 39 14 Reference Voltage and Reference Current Generation ...................... 40 15 Reset Function (Pin RESQ and Pin RESQ2) ........................................ 41 16 Watchdog Function ............................................................................... 47
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17 LIN/ISO 9141 Interfaces ......................................................................... 54 18 Voltage/Current Sources (IASGx Sources) ......................................... 58 19 AMUX (Analog Multiplexer for Voltage Measurements) ..................... 62 20 UZP Buffer .............................................................................................. 65 21 Chip Temperature Measurement .......................................................... 67 22 Serial Interface Commands ................................................................... 68
22.1 Overview ............................................................................................................68 22.2 Set Commands ..................................................................................................70 22.3 Serial Interface Status Register .........................................................................74
23 Test Mode ............................................................................................... 76 24 Application Circuits ............................................................................... 77 25 Ordering Information ............................................................................. 79 26 Package Information ............................................................................. 79 27 Revision History ..................................................................................... 80
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4929B-AUTO-01/07

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